User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 55
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
VREF Source Considerations
The VREF pins for HSTL signaling can be from an internal or external source. The user should choose
based system design needs. The reference source is selected using the slcr.GPIOB_CTRL
[VREF_SW_EN] register bit.
2.6 PS–PL AXI Interfaces
The PS side of the AXI interfaces are based on the AXI 3 interface specification. Each interface
consists of multiple AXI channels. The interfaces are summarized in Table 2-6. Over a thousand
signals are used to implement these nine PL AXI interfaces.
Note: The PL level shifters must be enabled via LVL_SHFTR_EN before PL logic communication can
occur, refer to section 2.7.1 Clocks and Resets.
2.7 PS–PL Miscellaneous Signals
The programmable logic interface group contains miscellaneous interfaces between PS and the PL.
An input is driven by the PL and an output is driven by the PS. Signals might have suffixes where an
'N' suffix indicates an active Low signal; otherwise the signal is active High. A 'TN’ suffix indicates an
active Low 3-state enable signal and is an output to the PL. Output signals to the PL are always driven
to either a High or Low level state.
PS-PL signal groups are identified in Table 2-7.
Table 2-6: PL AXI Interfaces
Interface
Name
Interface Description Master Slave Signals
M_AXI_GP0
General Purpose (AXI_GP)
PS PL Chapter 5, Interconnect has a
section to describe each of these
interfaces.
The AXI signals are listed
individually in section 5.6 PS-PL
AXI Interface Signals.
The AXI_ACP interface is also
described in multiple places in
Chapter 3, Application
Processing Unit, including section
3.5.1 PL Co-processing
Interfaces.
The PS interconnect is shown in
Figure 5-1.
M_AXI_GP1 PS PL
S_AXI_GP0
General Purpose (AXI_GP)
PL PS
S_AXI_GP1 PL PS
S_AXI_ACP
Accelerator Coherency Port,
cache-coherent transaction (ACP)
PL PS
S_AXI_HP0
High Performance ports (AXI_HP) with
read/write FIFOs and two dedicated
memory ports on DDR controller and
a path to the OCM. The AXI_HP
interfaces are known also as AFI.
PL PS
S_AXI_HP1 PL PS
S_AXI_HP2 PL PS
S_AXI_HP3 PL PS