User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 561
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
TxHPB. When the controller exits sleep mode, can.MSR[SLEEP] is set to
0
by the hardware and an
interrupt can be generated.
The CAN controller enters Sleep mode from Configuration mode when the LBACK bit in MSR is
0
, the
SLEEP bit in MSR is 1, and the CEN bit in SRR is 1. The CAN controller enters Sleep mode only when
there are no pending transmission requests from either the TX FIFO or the TX High Priority Buffer.
The CAN controller enters Sleep mode from Normal mode only when the SLEEP bit is 1, the CAN bus
is idle, and there are no pending transmission requests from either the TX FIFO or TX High Priority
Buffer.
When another node transmits a message, the CAN controller receives the transmitted message and
exits Sleep mode. When the controller is in Sleep mode, if there are new transmission requests from
either the TX FIFO or the TX High Priority Buffer, these requests are serviced, and the CAN controller
exits Sleep mode. Interrupts are generated when the CAN controller enters Sleep mode or wakes up
from Sleep mode. From sleep mode, the CAN controller can enter either the Configuration or Normal
modes.
Loop Back Mode (Diagnostics)
Loop back mode is used for diagnostic purposes. When in loop back mode, the controller must only
be programmed to enter
conf
iguration mode or issue reset. In loop back mode:
• The controller transmits a recessive bitstream onto the CAN_TX bus signal.
• Tx messages are internally looped back to the Rx line and are acknowledged.
• Tx messages are not sent on the CAN_TX bus signal.
• The controller receives all message that it transmits.
• The controller does not receive any messages transmitted by other CAN nodes.
Snoop Mode (Diagnostics)
Snoop mode is used for diagnostic purposes. When in snoop mode, the controller must only be
programmed to enter
conf
iguration mode or be held in reset. In snoop mode:
• The controller transmits a recessive bitstream onto the CAN bus.
• The controller does not participate in normal bus communication.
• The controller receives messages that are transmitted by other CAN nodes.
• Software can program acceptance
f
ilters to dynamically enable/disable and change criteria. Error
counters are disabled and cleared to 0. Reads to error counter registers return 0.
Mode Transitions
The supported mode transitions are shown in Figure 18-3. The transitions are primarily controlled by
the resets, the CEN bit, the MSR register settings, and a hardware wake-up mechanism.
To enter normal mode from configuration mode:
• Clear can.MSR[LBACK, SNOOP, SLEEP] = 0