User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 565
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
18.2.3 Message Buffering
Rx Messages
The RxFIFO can store up to 64 Rx CAN messages that are received and optionally filtered. Rx
messages that pass any of the acceptance filters are stored in the RxFIFO. When no acceptance filter
has been selected, all received messages are stored in the RxFIFO. Software reads these messages as
described in 18.3.7 Read Messages from RxFIFO.
A timestamp is added to each successfully stored Rx message. A free running 16-bit counter is
clocked using the CAN bit time clock. The rules for time stamping an Rx message are:
• The counter rolls over. There is no status bit to indicate that the roll over condition occurred.
• The timestamp included when a Rx message is successfully collected. The sampling of the
counter takes place at the last bit of EOF.
•The counter is cleared when CEN=0 or by software writing a 1 to the can.TCR register.
Software must read all four registers of an Rx message in the RxFIFO, regardless of how many data
bytes are in the message. The first word is read using the RXFIFO_ID register and contains the
identifier of the received message (IDR). The second word is read using the RXFIFO_DLC register and
contains the 16-bit timestamp and data length code (DLC) field. The third and fourth words contain
data word 1 (DW1R) and data word 2 (DW2R).
Writes to the RxFIFO registers are ignored. Read data from an empty RxFIFO are invalid and might
generate an interrupt.
The messages in the RxFIFO are retained even if the CAN controller enters Bus off state or
Configuration mode.
27-0 Reserved 0
Reads from this field return 0s.
Writes to this field should be 0s.
Data Word 1
DW1R[31:24] DB0[7:0] 0 Data Byte 0
DW1R[23:16] DB1[7:0] 0 Data Byte 1
DW1R[15:8] DB2[7:0] 0 Data Byte 2
DW1R[7:0] DB3[7:0] 0 Data Byte 3
Data Word 2
DW2R[31:24] DB4[7:0] 0 Data Byte 4
DW2R[23:16] DB5[7:0] 0 Data Byte 5
DW2R[15:8] D6[7:0] 0 Data Byte 6
DW2R[7:0] DB7[7:0] 0 Data Byte 7
Table 18-3: CAN Message Word Register Bit Fields (Cont’d)
Bits Name
Default
Value
Description