User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 566
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
Tx Messages
The controller has a configurable TxFIFO that software can use buffer up to 64 Tx CAN messages. The
controller also has a high priority transmit buffer (Tx HPB), with storage for one message. When a
higher priority message needs to be sent, software writes the message to the high priority transmit
buffer when it is available. The message in the TxHPB has higher priority over messages in the TxFIFO.
When arbitration loss or errors occur during the transmission of a message, the controller tries to
retransmit the message. No subsequent message, even a newer, higher priority message is
transmitted until the original message is transmitted without errors or arbitration loss.
The controller transmits the message starting with bit 31 of the IDR word. After the identifier word
is transmitted, the DLCR word is transmitted. This is followed by the data bytes in this order: DB0,
DB1, ... DB7. The last bit in the data portion of the message is DB7, bit 0. See Table 18-2, page 563.
The status bit, can.ISR[TXOK] is set = 1 after the controller successfully transmits a message from
either the TxFIFO or TxHPB.
The messages in the TxFIFO and TxHPB are retained even if the CAN controller enters Bus off state or
Configuration mode.
The message format is described in 18.2.2 Message Format.
Reads from RxFIFO
All 16 bytes must be read from the RxFIFO to receive the complete message. The first word read
(4 bytes) returns the identifier of the received message (IDR). The second read returns the 16-bit
receive time stamp and data length code (DLC) field of the received message (DLCR). The third read
returns data word 1 (DW1R), and the fourth read returns data word 2 (DW2R).
A free running 16-bit counter provides a time stamp relative to the time the message was
successfully received.
All four words must be read for each message, even if the message contains less than eight data
bytes. Write transactions to the RxFIFO are ignored. Reads from an empty RxFIFO return invalid data
and generates an Rx Underflow interrupt.
Rx and Tx Error Counters
When an Rx or Tx error occurs, the associated error counters in the protocol engine (see section
18.2.6 Protocol Engine) are incremented. The two error counters are 8 bits wide and are read using
the read-only can.ECR register, bit fields REC and TEC.
The Rx and Tx counters are reset when any the these situations occur:
•After a 1 is written to can.SRR[SRST] field = 1. This bit write is self-clearing.
•Anytime can.SRR[CEN] = 0 (configuration mode).
• When the controller enters Bus Off state.