User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 569
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
3. Clear TxFIFO watermark interrupt. Write a 1 to can.ICR[13].
4. Read TxFIFO watermark status. Read can.ISR[13].
5. Enable TxFIFO watermark interrupt. Write a 1 to can.IER[13].
Example: Program TxFIFO Empty Interrupt (14)
The following steps can be used to control the TxFIFO empty interrupt:
1. Disable TxFIFO empty interrupt. Write a 1 to can.IER[14].
2. Clear TxFIFO empty interrupt. Write a 1 to can.ICR[14].
3. Enable TxFIFO empty interrupt. Write a 1 to can.IER[14].
4. Read TxFIFO empty status. Read can.ISR[14]. It indicates the status whether TxFIFO is empty or
not.
18.2.5 Rx Message Filtering
To filter Rx messages, configure and enable up to four acceptance filters with acceptance mask and
ID registers to determine whether to store messages in the RxFIFO, or to acknowledge and discard
them.
Acceptance filtering is performed in the following sequence:
1. The incoming identifier is masked with the bits in the Acceptance Filter Mask register.
2. The Acceptance Filter ID register is also masked with the bits in the Acceptance Filter Mask
register.
3. Both resulting values are compared.
4. If both these values are equal, then the message is stored in the RxFIFO.
5. Acceptance filtering is processed by each of the defined filters. If the incoming identifier passes
through any acceptance filter, then the message is stored in the RxFIFO.
Acceptance Filter Enable
The Acceptance Filter register (AFR) defines which acceptance filters to use. It includes four enable
bits that correspond to the four acceptance filters. Each Acceptance Filter ID register (AFIR) and
Acceptance Filter Mask register (AFMR) pair is associated with a use acceptance filter (UAF) bit.
When the UAF bit is 1, the corresponding acceptance filter pair is used for acceptance filtering.
When the UAF bit is 0, the corresponding acceptance filter pair is not used for acceptance filtering.
To modify an acceptance filter pair in normal mode, the corresponding UAF bit in this register must
first be set to 0. After the acceptance filter is modified, the corresponding UAF bit must be set to 1
for the filter to be enabled.
The UAF bits in the can.AFR register enable the Rx acceptance filters:
• If all UAF bits are set to 0, then all received messages are stored in the RxFIFO.
• If the UAF bits are changed from a 1 to 0 during reception of a CAN message, the message will
not be stored in the RxFIFO.