User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 579
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
18.4 System Functions
18.4.1 Clocks
The controller and I/O interface are driven by the reference clock (CANx_REF_CLK). The controller's
interconnect also requires an APB interface clock. The APB interconnect clock (CPU_1x) always comes
from the PS clock subsystem.
The reference clock normally comes from the PS clock subsystem, but it can alternatively be driven
by an external clock source via any available MIO pin. The reference clock is used by the protocol
engine, the baud rate generator, and the datapath. The controllers share the same reference clock
frequency from the PS clock subsystem. If the reference clock is from an MIO pin, then the
frequencies can be different.
CPU_1x Clock
Refer to Chapter 25, Clocks, for general clock programming information. The CPU_1x clock runs
asynchronous to the CAN reference clock.
Reference Clock
CAN_REF_CLK is normally sourced from the PS clock subsystem, but it can alternatively be driven by
an external clock source via an MIO pin. Internally, the PS has three PLLs and two clock divider pairs.
The clock source choice, PS clock subsystem or external MIO pin, is controlled by the
CAN_MIOCLK_CTRL register.
The CAN clocks in the PS are controlled by slcr.CAN_CLK_CTRL. The generation of the CAN reference
clock by the PS is described in section The Quad-SPI clock is divided down by at least two using the
Quad-SPI baud rate divider, see section 12.4.1 Clocks. In master mode, the SPI clock is divided down
by at least four using the SPI baud rate divider, see section 17.4.2 Clocks.. There is one clock
Receive FIFO RXFIFO_ID
RXFIFO_DLC
RXFIFO_DATA1
RXFIFO_DATA2
Read received message.
Acceptance Filter AFR
AFMR[4:1]
AFIR[4:1]
Configure and control the four acceptance
filters.
System level slcr.CAN_CLK_CTRL
slcr.CAN_MIOCLK_CTRL
slcr.CAN_RST_CTRL
A controller reset and clock control.
Table 18-6: CAN Register Overview (Cont’d)
Function
Register Names
(CAN registers, except
where noted)
Overview