User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 58
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
2.7.5 DMA Req/Ack Signals
There are four sets of DMA controller flow control signals for use by up to four PL slaves connected
via the M_AXI_GP interfaces (see Table 2-11). These four sets of flow control signals correspond to
DMA channels 4 through 7, see
Chapter 9, DMA Controller.
2.8 PL I/O Pins
A summary of the PL I/O pins is shown in Table 2-13. Refer to the applicable Zynq-7000 AP SoC data
sheet and Zynq-7000 AP SoC packaging and pin documents for more information.
For more information on multi-gigabit serial transceivers pins, see the Pin Description and Design
Guidelines section in UG476
, 7 Series FPGAs GTX Transceivers User Guide. (Four to sixteen
transceivers are available in the Kintex-based Zynq 7z030, 7z035, 7z045, and 7z100 devices.)
7z007s and 7z010 Device Notice
Devices in CLG225 packages (7z010 dual core and 7z007s single core devices) have fewer pins than
the other Zynq-7000 AP SoC devices. For these devices, DXN is tied to ground, Bank 34 has 8 I/Os,
and Bank 35 has 46 I/Os. There are also only four pairs of XADC signals.
Table 2-11: PL AXI Idle, DDR Urgent/Arb and SRAM Interrupt Signals
Type PL Signal Name I/O Destination Reference
Idle PL AXI Interfaces FPGAIDLEN I
Central interconnect
clock disable logic
Central Interconnect Clock Disable in
section 25.1.4 Power Management
DDR Urgent Signal DDRARB[3:0] I
DDR memory
controller
Chapter 10, DDR Memory Controller
SRAM EMIOSRAMINTIN I
Static memory
controller interrupt
Chapter 11, Static Memory
Controller
Table 2-12: PL DMA Signals
Type Signal PL Signal Name I/O Reference
Clock and Reset Clock DMA[3:0]ACLK I 9.2.7 PL Peripheral Request Interface
Request
Ready DMA[3:0]DRREADY O
Chapter 9, DMA Controller
Valid DMA[3:0]DRVALID I
Type DMA[3:0]DRTYPE[1:0] I
Last DMA[3:0]DRLAST I
Acknowledge
Ready DMA[3:0]DAREADY I
Valid DMA[3:0]DAVALID O
Type DMA[3:0]DATYPE[1:0] O