User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 580
UG585 (v1.11) September 27, 2016
Chapter 18: CAN Controller
generator in the PS for both CAN controllers. If an MIO pins is used instead, the selected MIO_PIN
Mux register is programmed as an input.
Example: Configure and Route Internal Clock for Reference Clock
Configure the clock and disable MIO path. Assume the PLL is operating at 1000 MHz and the
required CAN reference clock is 24 MHz (23.8095 MHz).
1. Program the clock subsystem. Write 0x0030_0E03 to the slcr.CAN_CLK_CTRL register:
a. Enable both CAN reference clocks.
b. Divide the I/O PLL clock by 42 (0x02A): DIVISOR0= 0x0E and DIVISOR1=0x03 used by both
controllers.
2. Disable the MIO path. Write 0x0000_0000 to the slcr.CAN_MIOCLK_CTRL register to select the
clock from the internal clock subsystem/PLL for both controllers.
Example: Source Controller Clock from MIO Pin
This example uses MIO pin 45 as a controller clock reference.
1. Configure MIO device pin. Write 0x0000_1200 to the slcr.MIO_PIN_45 register:
a. Route MIO pin 45 to the GPIO controller (this is overridden in the next step).
b. Disable the output driver (TRI_ENABLE = 1).
c. LVCMOS18 (refer to the register definition for other voltage options).
d. Slow CMOS edge (benign setting).
e. Enable internal pull-up resistor.
f. Disable HSTL receiver.
2. Enable MIO path. Write to the slcr.CAN_MIOCLK_CTRL register to override the MIO PIN register
setting that was written in the previous step.
Write a 1 to slcr.CAN_MIOCLK_CTRL[CANx__REF_SEL] and write the desired MIO pin number into
the slcr.CAN_MIOCLK_CTRL[CANx_MUX] bit field to match the pin in the previous step.
18.4.2 Resets
The effects for each reset type are summarized in Table 18-7.
Table 18-7: CAN Reset Effects
Name
APB
Interface
Rx and Tx
FIFOs
Protocol
Engine
Control and
Status
Registers
Acceptance Filters
(ID and Mask)
Local CAN Reset
can.SRR[SRST]
Yes Yes Yes Yes No
PS Reset Subsystem
slcr.CAN_RST_CTRL[CANx_CPU1X_RST]
Yes Yes Yes Yes No