User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 586
UG585 (v1.11) September 27, 2016
Chapter 19: UART Controller
The baud rate generator can use either the master clock signal, uart_ref_clk, or the master clock
divided by eight, uart_ref_clk/8. The clock signal used is selected according to the value of the CLKS
bit in the Mode register (uart.mode_reg0). The resulting selected clock is termed sel_clk in the
following description.
The sel_clk clock is divided down to generate three other clocks: baud_sample, baud_tx_rate, and
baud_rx_rate. The baud_tx_rate is the target baud rate used for transmitting data. The baud_rx_rate
is nominally at the same rate, but gets resynchronised to the incoming received data. The
baud_sample runs at a multiple ([BDIV] + 1) of baud_rx_rate and baud_tx_rate and is used to
over-sample the received data.
The sel_clk clock frequency is divided by the CD field value in the Baud Rate Generator register to
generate the baud_sample clock enable. This register can be programmed with a value between 1
and 65535.
The baud_sample clock is divided by [BDIV] plus 1. BDIV is a programmable field in the Baud Rate
Divider register and can be programmed with a value between 4 and 255. It has a reset value of 15,
inferring a default ratio of 16 baud_sample clocks per baud_tx_clock / baud_rx_rate.
Thus the frequency of the baud_sample clock enable is shown in Equation 19-1.
Equation 19-1
The frequency of the baud_rx_rate and baud_tx_rate clock enables is show in Equation 19-2.
Equation 19-2
IMPORTANT: It is essential to disable the transmitter and receiver before writing to the Baud Rate
Generator register (uart.Baud_rate_gen_reg0), or the baud rate divider register
(uart.Baud_rate_divider_reg0). A soft reset must be issued to both the transmitter and receiver before
they are re-enabled.
Some examples of the relationship between the uart_ref_clk clock, baud rate, clock divisors (CD and
BDIV), and the rate of error are shown in Table 19-1. The highlighted entry shows the default reset
X-Ref Target - Figure 19-3
Figure 19-3: UART Board Rate Generator
uart.mode_reg0[0]
Divide
by 8
CD
Programmable
Divider
sel_clk
UART Ref clock
Rx and Tx
Baud rate
UG585_c19_03_071912
0
1
Sel
Clk
uart.Baud_rate_gen_reg0[15:0]
BDIV
Programmable
Divider
uart.Baud_rate_divider_reg0[7:0]
Baud
Sample
baud_sample
sel_clk
CD
---------------
=
baud_rate
sel_clk
CD BDIV 1+()×
------------------------------------
=