User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 588
UG585 (v1.11) September 27, 2016
Chapter 19: UART Controller
The transmit module shifts out the start bit, data bits, parity bit, and stop bits as a serial data stream.
Data is transmitted, least significant bit first, on the falling edge of the transmit baud clock enable
(baud_tx_rate). A typical transmitted data stream is illustrated in Figure 19-4.
The uart.mode_reg0[CHRL] register bit selects the character length, in terms of the number of data
bits. The uart.mode_reg0[NBSTOP] register bit selects the number of stop bits to transmit.
19.2.6 Receiver FIFO
The RxFIFO stores data that is received by the receiver serial shift register. The RxFIFO’s maximum
data width is eight bits.
When data is loaded into the RxFIFO, the RxFIFO empty flag is cleared and this state remains Low
until all data in the RxFIFO has been transferred through the APB interface. Reading from an empty
RxFIFO returns zero.
The RxFIFO full status (Chnl_int_sts_reg0 [RFUL] and Channel_sts_reg0 [RFUL] bits) indicates that the
RxFIFO is full and prevents any further data from being loaded into the RxFIFO. When a space
becomes available in the RxFIFO, any character stored in the receiver will be loaded.
A threshold trigger (RTRIG) can be setup on the RxFIFO fill level. The Receiver Trigger Level register
(Rcvr_FIFO_trigger_level0) can be used to setup this value, such that the trigger is set when the
RxFIFO fill level transitions this programmed value. The Range is 1 to 63.
19.2.7 Receiver Data Capture
The UART continuously over-samples the UARTx_RxD signal using UARTx REF_CLK and the clock
enable (baud_sample). When the samples detect a transition to a Low level, it can indicate the
beginning of a start bit. When the UART senses a Low level at the UART_RxD input, it waits for a count
of half of BDIV baud rate clock cycles, and then samples three more times. If all three bits still
indicate a Low level, the receiver considers this to be a valid start bit, as illustrated in Figure 19-5 for
the default BDIV of 15.
X-Ref Target - Figure 19-4
Figure 19-4: Transmitted Data Stream
baud_tx_rate
TXD
D0 D1 D2 D3 D4 D5 D6 D7 PA S
UG585_c19_04_020613
START
STOP
X-Ref Target - Figure 19-5
Figure 19-5: Default BDIV Receiver Data Stream
baud_sample
rxd
12345678
Start Bit
9 10111213141516 1 2
Data (LSB)
UG585_c19_05_022612