User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 59
UG585 (v1.11) September 27, 2016
Chapter 2: Signals, Interfaces, and Pins
CAUTION! The allowable Vin High level voltages are defined in the Zynq-7000 AP SoC data sheets.
Damage to the input buffer can occur when the limits are exceeded.
Table 2-13: PL Pin Summary
Group Name Type Description
User I/O Pins
IO_LXXY_#,
IO_XX_#
I/O
Most user I/O pins are capable of differential signaling and can be
implemented as pairs. The top and bottom I/O pins are always
single ended.
Multi-Gigabit
Serial
Transceivers
MGTXRX[P,N] I
Differential receive and transmit ports. Multi-Gigabit Serial
Transceiver pins. Four transceivers are available in the Zynq-7000
AP SoC 7z030 device and 16 in the 7z035, 7z045 and 7z100 devices.
MGTXTX[P,N] O
MGTAVCC_G# I
1.0V analog power-supply pin for receiver and transmitter internal
circuits.
MGTAVTT_G# I 1.2V analog power-supply pin for the transmit driver.
MGTVCCAUX_G# I 1.8V auxiliary analog Quad PLL voltage supply for the transceivers.
MGTREFCLK0/1P I Positive differential reference clock for the transceivers.
MGTREFCLK0/1N I Negative differential reference clock for the transceivers.
MGTAVTTRCAL N/A Precision reference resistor pin for internal calibration termination.
MGTRREF I Precision reference resistor pin for internal calibration termination.
PL JTAG
PL_TCK, PL_TMS,
PL_TDI, PL_TDO
I/O See Chapter 27, JTAG and DAP Subsystem.
Configuration
DONE, INIT_B,
PROGRAM_B
I/O Refer to the 7-series documentation.
CFGBVS I
Pre-configuration I/O standard type for the dedicated
configuration bank 0.
PUDC_B I
Active Low input enables internal pull-ups during configuration on
all SelectIO pins.
XADC
VP, VN I Dedicated differential analog inputs.
VREFP, VREFN N/A Reference input (1.25V) and ground.
AD[15:0]P,
AD[15:0]N
I 16 differential auxiliary analog inputs.
Multi-function
MRCC I
Clock capable I/Os driving BUFRs, BUFIOs, BUFGs and
MMCMs/PLLs. In addition, these pins can drive the BUFMR for
multi-region BUFIO and BUFR support. These pins become regular
user I/Os when not needed as a clock.
SRCC I
Clock capable I/Os driving BUFRs, BUFIOs and MMCMs/PLLs. These
pins become regular user I/Os when not needed for clocks.
T[3:0] I Four memory byte groups.
T[3:0]_DQS I DDR DQS strobe pin that belongs to the memory byte group T0-T3.
Temperature DXP, DXN I Temperature-sensing diode pins.
Reserved
RSVDVCC I Tie to V
CCO_0
.
RSVDGND I Tie to ground.