User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 594
UG585 (v1.11) September 27, 2016
Chapter 19: UART Controller
• DMSI: indicates a change of logic level on the DCD, DSR, RI or CTS modem flow control signals.
This includes High-to-Low and Low-to-High logic transitions on any of these signals.
FIFO Interrupts
The status bits for the FIFO interrupts listed in Table 19-2 are illustrated in Figure 19-9. These
interrupt status bits are in the Channel Status (uart.Channel_sts_reg0) and Channel Interrupt Status
(uart.Chnl_int_sts_reg0) registers with the exception that the [TOVR] and [ROVR] bits are not part of
the uart.Channel_sts_reg0 register.
The FIFO trigger levels are controlled by these bit fields:
• uart.Rcvr_FIFO_trigger_level0[RTRIG], a 6-bit field
• uart.Tx_FIFO_trigger_level0[TTRIG], a 6-bit field
19.2.11 Modem Control
The modem control module facilitates the control of communication between a modem and the
UART. It contains the Modem Status register, the Modem Control register, the DMSI bit in interrupt
status register, and FDELT in the channel status register. This event is triggered whenever the DCTS,
DDSR, TERI, or DDCD in the modem status register are being set.
The read-only Modem Status register is used to read the values of the clear to send (CTS), data carrier
detect (DCD), data set ready, (DSR) and ring indicator (RI) modem inputs. It also reports changes in
any of these inputs and indicates whether automatic flow control mode is currently enabled. The bits
in the Modem Status register are cleared by writing a 1 to the particular bit.
The read/write only Modem Control register is used to set the data terminal ready (DTR) and request
to send (RTS) outputs, and to enable the Automatic Flow Control Mode register.
By default, the automatic flow control mode is disabled, meaning that the modem inputs and
outputs work completely under software control. When the automatic flow control mode is enabled
by setting the FCM bit in the Modem Control register, the UART transmission and reception status is
automatically controlled using the modem handshake inputs and outputs.
X-Ref Target - Figure 19-9
Figure 19-9: UART RxFIFO and TxFIFO Interrupt
TxFIFO (64 bytes)
Full Interrupt
[TFUL]
Empty Interrupt
[TEMPTY]
Trigger Interrupt
[TTRIG]
RxFIFO (64 bytes)
Full Interrupt
[RFUL]
Overflow Interrupt
[ROVR]
Trigger Interrupt
[RTRIG]
Nearly Full Interrupt
[TNFUL]
Empty Interrupt
[REMPTY]
UG585_c19_12_102912
Overflow Interrupt
[TOVR]
uart.Rcvr_FIFO_trigger_level0
uart.Tx_FIFO_trigger_level0