User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 597
UG585 (v1.11) September 27, 2016
Chapter 19: UART Controller
5. Configure interrupts: Interrupts are used to manage the Rx/Tx FIFOs in all modes. Refer to
section 19.2.10 Status and Interrupts and the program example in section 19.3.5 RxFIFO Trigger
Level Interrupt.
6. Configure modem controls (optional): Polling and interrupt driven options. Refer to section
19.2.11 Modem Control.
7. Manage transmit and receive data: Polling and interrupt driven handlers are supportable. Refer
to sections 19.3.3 Transmit Data and 19.3.4 Receive Data.
19.3.2 Configure Controller Functions
Example: Configure Controller Functions
This example configures the character frame, the baud rate, the FIFO trigger levels, the Rx timeout
mechanism, and enables the controller. All of these steps are necessary after a reset, but not
necessary between enabling and disabling the controller.
1. Configure UART character frame. Write 0x0000_0020 into the uart.mode_reg0:
a. Disables clock pre-divider, UART_REF_CLK/8: [CLKS] = 0
b. Selects 8-bit character length: [CHRL] = 00
c. Selects no parity: [PAR] = 100
d. Selects 1 stop bit: [NBSTOP] = 00
e. Selects normal channel mode (Mode Switch): [CHMODE] = 00
2. Configure the Baud Rate. Write to three registers: uart.Control_reg0, uart.Baud_rate_gen_reg0,
and uart.Baud_rate_divider_reg0. Examples for the calculated CD and BDIV values are shown in
table Table 19-1, page 587. The baud rate generator is described in section 19.2.3 Baud Rate
Generator.
a. Disable the Rx path: set uart.Control_reg0 [RXEN] = 0 and [RXDIS] = 1.
b. Disable the Txpath: set uart.Control_reg0 [TXEN] = 0 and [TXDIS] = 1.
c. Write the calculated CD value into the uart.Baud_rate_gen_reg0 [CD] bit field.
d. Write the calculated BDIV value into the uart.Baud_rate_divider_reg0 [BDIV] bit value.
e. Reset Tx and Rx paths: uart.Control_reg0 [TXRST] and [RXRST] = 1. These bits are
self-clearing.
f. Enable the Rx path: Set [RXEN] = 1 and [RXDIS] = 0.
g. Enable the Tx path: Set [TXEN] = 1 and [TXDIS] = 0.
3. Set the level of the RxFIFO trigger level. Write the trigger level into the
uart.Rcvr_FIFO_trigger_level0 register.
°
Option a: Enable the Rx trigger level: Write a value of 1 to 63 into the [RTRIG] bit field.
°
Option b: Disable the Rx trigger level: Write 0 into the [RTRIG] bit field.
4. Enable the Controller. Write 0x0000_0117 into the uart.Control_reg0 register.
a. Reset Tx and Rx paths: uart.Control_reg0 [TXRST] and [RXRST] = 1. These bits are
self-clearing.
b. Enables the Rx path: [RXEN] = 1 and [RXDIS] = 0.