User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 598
UG585 (v1.11) September 27, 2016
Chapter 19: UART Controller
c. Enables the Tx path: [TXEN] = 1 and [TXDIS] = 0.
d. Restarts the Receiver Timeout Counter: [RSTTO] = 1.
e. Does not start to transmit a break: [STTBRK] = 0.
f. Stop Break transmitter: [STPBRK] = 1
5. Program the Receiver Timeout Mechanism. Write the timeout value into the
uart.Rcvr_timeout_reg0 register. Refer to Receiver Timeout Mechanism, page 589.
a. To enable the timeout mechanism, write a value of 1 to 255 into the [RSTTO] bit field.
b. To disable the timeout mechanism, write a 0 into the [RSTTO] bit field.
19.3.3 Transmit Data
Software can used polling or interrupts to control the flow of data to the TxFIFO and RxFIFO.
Note: When the TxFIFO Empty status is true, software can write 64 bytes (the size of the TxFIFO)
without checking the TxFIFO status. In reality, software can write more than 64 bytes when the
transmitter is active because while the software is writing data to the TxFIFO, the controller is
removing data and serializing it onto the TxD signal.
Example: Transmit Data using the Polling Method
In this example, the software can choose to fill the TxFIFO until the Full status bit is set or wait for the
TxFIFO to be empty (and write up to 64 bytes). The software can always write a byte when the TxFIFO
is nearly full.
1. Check to see if the TxFIFO is empty. Wait until uart.Channel_sts_reg0[TEMPTY] = 1.
2. Fill the TxFIFO with data. Write 64 bytes of data to the uart.TX_RX_FIFO0 register.
3. Write more data to the TxFIFO. There are two methods:
Option A: Check to see if the TxFIFO has room to another byte of data (i.e., the TxFIFO is not
full): Read uart.Channel_sts_reg0 [TFUL] until it equals 0. When [TFUL] = 0, write a single byte of
data into the TxFIFO and then read [TFUL] again.
Option B: Wait until the TxFIFO goes empty. Read uart.Channel_sts_reg0 [TEMPTY] until it
equals 1, then go to step 2 to fill the TxFIFO with 64 bytes of data.
Example: Transmit Data using the Interrupt Method
This example initially fills the TxFIFO in a similar way as the polling method. Then, software enables
the TxFIFO Empty interrupt to alert the software to fill-up the TxFIFO again.
1. Disable the TxFIFO Empty interrupt. Write a 1 to uart.Intrpt_dis_reg0 [TEMPTY].
2. Fill the TxFIFO with data. Write 64 bytes of data to the uart.TX_RX_FIFO0 register.
3. Check to see if the TxFIFO has room to another byte of data (i.e., the TxFIFO is not full): read
uart.Channel_sts_reg0 [TFUL] until it equals 0. When [TFUL] = 0, write a single byte of data into
the TxFIFO and then read [TFUL] again.
4. Repeat step 2 and 3. Repeat until uart.Channel_sts_reg0 [TFUL] is not set.