User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 60
UG585 (v1.11) September 27, 2016
Chapter 3
Application Processing Unit
3.1 Introduction
3.1.1 Basic Functionality
The application processing unit (APU), located within the PS, contains one processor for single-core
devices or two processors for dual-core devices. These are ARM® Cortex™-A9 processors with NEON
co-processors connected in an MP configuration sharing a 512 KB L2 cache. Each processor is a
high-performance and low-power core that implements two separate 32 KB L1 caches for instruction
and data. The Cortex-A9 processor implements the ARM v7-A architecture with full virtual memory
support and can execute 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit
Java™ byte codes in the Jazelle state. The NEON™ coprocessor media and signal processing
architecture adds instructions that target audio, video, image and speech processing, and 3D
graphics. These advanced single instruction multiple data (SIMD) instructions are available in both
ARM and Thumb states. A block diagram of the APU is shown in Figure 3-1.
The Cortex-A9 processor(s) within the APU are organized in an MP configuration with a snoop
control unit (SCU) responsible for maintaining L1 cache coherency between the two processors and
the ACP interface from the PL. To increase performance, there is a shared unified 512 KB level-two
(L2) cache for instruction and data. In parallel to the L2 cache, there is a 256 KB on-chip memory
(OCM) module that provides a low-latency memory.
An accelerator coherency port (ACP) facilitates communication between the programmable logic (PL)
and the APU. This 64-bit AXI interface allows the PL to implement an AXI master that can access the
L2 and OCM while maintaining memory coherency with the CPU L1 caches.
The unified 512 KB L2 cache is 8-way set-associative and allows you to lock the cache content on a
line, way, or master basis. All accesses through the L2 cache controller can be routed to the DDR
controller or can be sent to other slaves in the PS or PL depending on their address. To reduce
latency to the DDR memory, there is a dedicated port from the L2 controller to the DDR controller.
Debug and trace capability is built into the two processor cores and interconnects as a part of the
CoreSight™ debug and trace system. You can control and interrogate the processor(s) and the
memory through the debug access port (DAP). Furthermore, 32-bit AMBA® trace bus (ATB) masters
from the processor(s) are funneled with other ATB masters, such as Instrumentation Trace Macrocell
(ITM) and Fabric Trace Monitor (FTM), to generate the unified PS trace through the on-chip
embedded trace buffer (ETB) or the trace-port interface units (TPIU).