User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 608
UG585 (v1.11) September 27, 2016
Chapter 20: I2C Controller
20.2.3 Slave Monitor Mode
This mode is meaningful only when the module is in master mode and bit SLVMON in the control
register is set. The host must set the MS and SLVMON bits and clear the RW bit in the Control
register. Also, it must initialize the Slave Monitor Pause register.
The master attempts a transfer to a particular slave whenever the host writes to the I2C Address
register. If the slave returns a NACK when it receives the address, the master waits for the time
interval established by the Slave Monitor Pause register and attempts to address the slave again. The
master continues this cycle until the slave responds with an ACK to its address or until the host clears
the SLVMON bit in the Control register. If the addressed slave responds with an ACK, the I2C
interface terminates the transfer by generating a STOP condition and a SLV_RDY interrupt.
20.2.4 Slave Mode
The I2C interface is set up as a slave by clearing the MS bit in the Control register. The I2C slave must
be given a unique identifying address by writing to the I2C address register. The SCL speed must also
be set up at least as fast as the fastest SCL frequency expected to be seen. When in slave mode, the
I2C interface operates as either a slave transmitter or a slave receiver.
Slave Transmitter
The slave becomes a transmitter after recognizing the entire slave address sent by the master and
when the R/W field in the last address byte sent is High. This means that the slave has been
requested to send data over the I2C bus and the host is notified of this through an interrupt through
an interrupt to the GIC (refer to Figure 20-1, page 605). At the same time, the SCL line is held Low to
allow the host to supply data to the I2C slave before the I2C master starts sampling the SDA line. The
host is notified of this event by setting the DATA interrupt flag.
At the same time, the SCL line is held Low to allow the host to supply data to the I2C slave before the
I2C master starts sampling the SDA line.
The host must supply data for transmission through the I2C data register so that the SCL line is
released and transfer continues. If it does not write to the I2C data register before the timeout period
expires, an interrupt is generated and a TO interrupt flag is set.
After the host writes to the I2C data register, the transfer continues by loading data in the FIFO while
the transfer is in progress. The amount of data loaded in the FIFO might be a known system
parameter or communicated in advance through a higher level protocol using the I2C bus.
When there are only two valid bytes left in the FIFO for transmission, an interrupt is generated and
the DATA interrupt flag is set. If the I2C master returns a NACK on the last byte transmitted from the
FIFO, an interrupt is generated, and the COMP interrupt flag is set as soon as the I2C master
generates a STOP condition.
The transfer must continue if the master acknowledges on the last byte sent out from the FIFO. At
that moment, the DATA interrupt flag is set. The TXDV flag in the Status register is cleared because
the FIFO is empty.