User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 609
UG585 (v1.11) September 27, 2016
Chapter 20: I2C Controller
If the I2C master terminates the transfer before all of the data in the FIFO is sent by the slave, the
host is notified, and the NACK interrupt flag is set while TXDV remains set and the Transfer Size
register indicates the remaining bytes in the FIFO. The host must set the CLR_FIFO bit in the Control
register to clear the FIFO and the TXDV bit.
Slave Receiver
The slave becomes a receiver after recognizing the entire slave address sent by the master and when
the R/W bit in the first address byte is Low. This means that the master is about to send one or more
data bytes to the slave over the I2C bus.
After a byte is acknowledged by the I2C slave, the RXDV bit in the Status register is set, indicating
that new data has been received. The host reads the received data through the I2C Data register. An
interrupt is generated and the DATA interrupt flag is set when there are only two free locations left
in the FIFO.
Whenever the I2C master generates a STOP condition, an interrupt is generated and the COMP
interrupt flag is set. The Transfer Size register then contains the number of bytes received that are
available in the FIFO. This number is decremented by the host on each read of the I2C Data register.
If the FIFO is full when one or more bytes are received by the I2C interface, an interrupt is generated
and the RX_OVF interrupt flag is set. The last byte received is not acknowledged and the data in the
FIFO is kept intact.
The HOLD bit can be set in the Control register to avoid overflow conditions when it is impossible to
respond to interrupts in a reasonable time. If the HOLD bit is set, the I2C interface keeps the SCL line
Low until the host clears resources for data reception. This prevents the master from continuing with
the transfer, causing an overflow condition in the slave. The host clears resources for data reception
by reading the data register.
If the HOLD bit is set and the I2C interface keeps the SCL line Low for longer than the timeout period,
an interrupt is generated and the TO interrupt flag is set.
20.2.5 I2C Speed
The main clock used within the I2C interface is the clock enable signal (see Figure 20-3).
• In slave mode, the clock enable is used to extract synchronization information for correct
sampling of the SDA line.
• In master mode, the clock enable is used to establish a time base for generating the desired SCL
frequency.