User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 613
UG585 (v1.11) September 27, 2016
Chapter 20: I2C Controller
e. Clear the FIFOs: Set i2c.Control_reg0[CLR_FIFO] = 1.
f. Program the clock divisors:
- Set i2c.Control_reg0[divisor_a] = 0.
- Set i2c.Control_reg0[divisor_b] = 50.
These divisors generate an I2C SCL of 99 KHz using the CPU_1X clock of 111 MHz. For further
details refer to section 20.2.5 I2C Speed.
2. Configure Timeout. Write 0x0000_00FF to the i2c.Time_out_reg0 register. Wait 255 SCL cycles
when the SCL is held Low, before generating a timeout interrupt.
20.3.3 Configure Interrupts
The interrupts are described in section 20.2.8 Status and Interrupts. The i2c.Intrpt_enable_reg0 register
has bits to enable the interrupt mask and i2c.Intrpt_disable_reg0 has bits to forcefully disable the
interrupts. Each pair of bits should be set mutually exclusive:
Example: Program Example to Configure Completion Interrupt
1. Enable the completion interrupt. Set the enable bit, clear the disable bit, and verify the mask
value:
a. Set i2c.Intrpt_enable_reg0[COMP] = 1.
b. Clear i2c.Intrpt_disable_reg0[COMP] = 0.
c. i2c.intrpt_mask_reg0[COMP] reads back = 1.
2. Disable the completion interrupt. Set the enable bit, clear the disable bit, and verify the mask
value:
a. Set i2c.Intrpt_disable_reg0[COMP] = 1.
b. Clear i2c.Intrpt_enable_reg0[COMP] = 0.
c. i2c.Intrpt_mask_reg0[COMP] reads back = 0.
3. Monitor completion interrupt. I2c.Interrupt_status_reg0 provides status of completion
interrupt.:
a. Read i2c.Interrupt_status_reg0 [COMP]. 1 indicates that an interrupt occurred.
4. Clear completion interrupt. Write 1 to the i2c.Interrupt_status_reg0[COMP] bit field.
20.3.4 Data Transfers
Transfers can be achieved in polled mode or interrupt driven mode. Limitation on data count while
performing a master read transfer is 255 bytes. Below are examples of read and write transfer in
Master mode and example for Slave Monitor mode. Refer to section 20.2.3 Slave Monitor Mode for
details.
Example: Master Read Using Polled Method
1. Set direction of transfer as read and clear the FIFOs. Write 0x41 to i2c.Control_reg0.