User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 615
UG585 (v1.11) September 27, 2016
Chapter 20: I2C Controller
5. Write the slave address. Write the address to the i2c.I2C_address_reg0 register.
6. Wait for data to be received into FIFO.
a. If read data count is greater than FIFO depth, wait for i2c.Interrupt_status_reg0 [DATA] = 1.
Read 14 bytes from FIFO. Decrement the read data count by 14 and if it is less than or equal
to the FIFO depth, clear i2c.Control_reg0[HOLD]
b. Otherwise, wait for i2c.Interrupt_status_reg0 [COMP] = 1 and read data from the FIFO based
on the read data count.
7. Check for completion of transfer. Check if read count reaches zero. Otherwise repeat from step
6.
Example: Master Write Using Interrupt Method
1. Set direction of transfer as write and clear the FIFO’s. Write 0x40 to i2c.Control_reg0.
2. Clear Interrupts. Read and write back the read value to i2c.Interrupt_status_reg0.
3. Enable Timeout, NACK, Tx Overflow, Arbitration lost, DATA, Completion interrupts. Write
0x24F to the i2c.Intrpt_en_reg0 register.
4. Enable bus HOLD logic. Set i2c.Control_reg0 [HOLD] if the write data count is greater than the
FIFO depth.
5. Calculate the space available in FIFO. Subtract the i2c.Transfer_size_reg0 value from the FIFO
depth.
6. Fill the data into FIFO. Write the data to i2c.I2C_data_reg0 based on the count obtained in
step 5.
7. Write the slave address. Write the address to the i2c.I2C_address_reg0 register.
8. Wait for data to be sent. Check for i2c.Interrupt_status_reg0 [COMP] to be set.
a. If further data is to be written, repeat steps 5, 6 and 8.
b. If there is no further data, set i2c.Control_reg0 [HOLD] = 0.
9. Wait for completion of transfer. Check for i2c.Interrupt_status_reg0 [COMP] to be set.
Example: Slave Monitor Mode
Slave monitor mode helps to monitor when the slave is in the busy state. The slave ready interrupt
occurs only when slave is not busy. This can be done only in master mode:
1. Select slave monitor mode and clear the FIFOs. Write 0x60 to i2c.Control_reg0.
2. Clear interrupts. Read and write back the read value to i2c.Interrupt_status_reg0.
3. Enable Interrupts. Set i2c.Intrpt_en_reg0 [SLV_RDY] = 1.
4. Set slave monitor delay. Set i2c.Slave_mon_pause_reg0 with 0xF.
5. Write the Slave Address. Write the address to the i2c.I2C_address_reg0 register.
6. Wait for slave to be ready. Poll on i2c.Interrupt_status_reg0 [SLV_RDY] = 1.