User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 62
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
3.1.2 System-Level View
The APU is the most critical component of the system that comprises the PS, the IP cores
implemented in the PL, and board-level devices such as the external memories and the peripherals.
The main interfaces through which the APU communicates to the rest of the system are two
interfaces through the L2 controller and an interface to the OCM that is parallel to the L2 cache. See
Figure 3-1.
All accesses from the dual/single Cortex-A9 MP system go through the SCU and all accesses from
any other master that requires coherency with the Cortex-A9 MP system also need to be routed
through the SCU using the ACP Port. All accesses that are not routed through the SCU are
non-coherent with the CPU and software has to explicitly handle the synchronization and coherency.
Accesses from the APU can target the OCM, DDR, PL, IOP slaves, or registers within the PS
sub-blocks. To minimize the latency to the OCM, a dedicated master port from the SCU provides
direct access by the processors and the ACP to the OCM, offering a latency that is even less than the
L2 cache.
All APU accesses to the DDR are routed through the L2 cache controller. To improve the latencies of
the DDR accesses, there is a dedicated master port from the L2 cache controller to the DDR memory
controller that allows all APU-DDR transactions to bypass the main interconnects which are shared
with the other masters. All other accesses from the APU that are neither OCM-bound nor
DDR-bound go through the L2 controller and are routed through the main interconnect using a
second port. The accesses that pass through the L2 cache controller do not have to be cacheable.
Exclusive access transactions from LDREX/SDREX instructions or ACP exclusive transactions in the
APU are described under Exclusive AXI Accesses in Chapter 5. As shown in Figure 3-2, the APU and
its sub-blocks all operate in the CPU_6x4x clock domain. The interfaces from the APU to the OCM
and to the main interconnects are all synchronous. The main interconnects can run at 1/2 or 1/3 of
the frequency of the CPU. The DDR block is on the DDR_3x clock domain and operates
asynchronously to the APU. The ACP port to the APU block includes a synchronizer and the PL master
that uses this port can have a clock that is asynchronous to the APU.