User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 621
UG585 (v1.11) September 27, 2016
Chapter 21: Programmable Logic Description
21.1.2 PL Resources by Device Type
The PL resources on a per-device type are summarized in Table 21-1.
Table 21-1: PL Resources by Device Type
Resource 7z007s 7z012s 7z014s 7z010 7z015 7z020 7z030 7z035 7z045 7z100
Logic Slices
Total 3,600
(1)
8,600
(1)
10,150
(1)
4,400 11,550 13,300 19,650 42,975 54,650 69,350
Type L 1,100 5,000 5,800 2,900 7,950 8,950 13,000 25,375 37,050 42,300
Type M 1,500 3,600 4,350 1,500 3,600 4,350 6,650 17,600 17,600 27,050
LUTs
Total 14,400 34,400 40,600 17,600 46,200 53,200 78,600 171,900 218,600 277,400
Flip-flops 28,800 68,800 81,200 35,200 92,400 106,400 157,200 343,800 437,200 554,800
Logic cells 23,000 55,000 65,000 28,160 73,920 85,120 125,760 275,040 349,760 443,840
LUTRAM
Kb
375 900 1,088 375 900 1,088 1,663 4,400 4,400 6,763
SRL Kb 188 450 544 188 450 544 831 2,200 2,200 3,381
Memory Resources
Block RAM
count
50
(2)
72
(2)
107
(2)
60 95 140 265 500 545 755
Kb 1,800 2,590 3,850 2,160 3,420 5,040 9,540 18,000 19,620 27,180
KB 220 320 480 240 380 560 1,060 2,250 2,180 3,020
Columns
per device
55655689912
Block
RAMs per
column
Varies,
usually
20
Varies,
usually
30
Varies,
usually
30
Varies,
usually
20
Varies,
usually
30
Varies,
usually
30
Varies,
usually
40
Varies,
usually
70
Varies,
usually
70
Varies,
usually
70
Clocking
MMCM/
PLL count
2342345888
DSPs (DSP48E1)
Count 66
(2)
120
(2)
170
(2)
80 160 220 400 900 900 2,020
Columns
per device
44544567715
DSPs per
column
Varies,
usually
40
Varies,
usually
60
Varies,
usually
60
Varies,
usually
40
Varies,
usually
60
Varies,
usually
60
Varies,
usually
80
Varies,
usually
140
Varies,
usually
140
Varies,
usually
140
Gigabit Transceivers
(3)
GTP 0400400000
GTX 00000048 or 16
(3)
8 or 16
(3)
16
PCIe
capable
no yes no no yes no yes yes yes yes
Select I/O
(4)
Bank count2342345888