User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 627
UG585 (v1.11) September 27, 2016
Chapter 21: Programmable Logic Description
e. Clocks
f. Debug interfaces
2. Configuration interface – connected to fixed logic within the PL configuration block, providing
PS control
a. PCAP
b. Configuration status
c. SEU
d. Program/Done/Init
For details on PS-PL interfaces refer to Chapter 2, Signals, Interfaces, and Pins.
Voltage Level Shifters
All of the signals between the PS and PL pass through voltage level shifters. The programming of
these level shifters is explained in section 2.4 PS–PL Voltage Level Shifter Enables.
21.3.2 SelectIO
Some highlights of the input/output functionality include:
• High-performance SelectIO technology with support for 1,866 Mb/s DDR3
• High-frequency decoupling capacitors within the package for enhanced signal integrity
• Digitally controlled impedance that can be 3-stated for lowest power, high-speed I/O operation
The number of I/O pins varies depending on device and package size. Each I/O is configurable and
can comply with a large number of I/O standards. With the exception of the supply pins and a few
dedicated configuration pins, all other PL pins have the same I/O capabilities, constrained only by
certain banking rules. The SelectIO resources in Zynq-7000 AP SoC devices are classed as either high
range (HR) or high performance (HP). The HR I/Os offer the widest range of voltage support, from
1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.2V to 1.8V.
All I/O pins are organized in banks, with 50 pins per bank. Each bank has one common V
CCO
output
supply, which also powers certain input buffers. Some single-ended input buffers require an
internally generated or an externally applied reference voltage (V
REF). There are two VREF pins per
bank (except configuration bank 0). A single bank can have only one V
REF voltage value.
Zynq-7000 AP SoC devices use a variety of package types to suit the needs of the user, including
small form factor wire-bond packages for lowest cost; conventional, high performance flip-chip
packages; and lidless flip-chip packages that balance smaller form factor with high performance. In
the flip-chip packages, the silicon device is attached to the package substrate using a
high-performance flip-chip process. Controlled ESR discrete decoupling capacitors are mounted on
the package substrate to optimize signal integrity under simultaneous switching of outputs (SSO)
conditions.