User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 628
UG585 (v1.11) September 27, 2016
Chapter 21: Programmable Logic Description
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure driving High towards
V
CCO
or Low towards ground, and can be put into a high-Z state. The system designer can specify the
slew rate and the output strength. The input is always active but is usually ignored while the output
is active. Each pin can optionally have a weak pull-up or a weak pull-down resistor.
Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input
pin pairs can optionally be terminated with a 100Ω internal resistor. All Zynq-7000 AP SoC devices
support differential standards beyond LVDS: HT, RSDS, BLVDS, differential SSTL, and differential
HSTL.
Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well
as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to
1,866 Mb/s for DDR3 interfacing applications.
3-State Digitally Controlled Impedance and Low-Power I/O Features
The 3-state digitally controlled impedance (T_DCI) can control the output drive impedance (series
termination) or can provide parallel termination of an input signal to V
CCO
or split (Thevenin)
termination to V
CCO
/2. This allows users to eliminate off-chip termination for signals using T_DCI. In
addition to board space savings, the termination automatically turns off when in output mode or
when 3-stated, saving considerable power compared to off-chip termination. The I/Os also have
low-power modes for IBUF and IDELAY to provide further power savings, especially when used to
implement memory interfaces.
I/O Logic
Input and Output Delay
All inputs and outputs can be configured as either combinatorial or registered. Double data rate
(DDR) is supported by all inputs and outputs. Any input and some outputs can be individually
delayed by up to 32 increments of 78 ps or 52 ps each.
Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by
configuration and can also be incremented or decremented while in use. ODELAY is only available for
HP Select I/O. It is not available for HR select I/Os. HP Select I/O pins are available in the 7z030,
7z035, 7z045, and 7z100 devices, refer to Table 21-1.
ISERDES and OSERDES
Many applications combine high-speed, bit-serial I/O with slower parallel operation inside the
device. This requires a serializer and deserializer (SerDes) inside the I/O structure. Each I/O pin
possesses an 8-bit IOSERDES (ISERDES and OSERDES) capable of performing serial-to-parallel or
parallel-to-serial conversions with programmable widths of 2, 3, 4, 5, 6, 7, or 8 bits. By cascading two
IOSERDES from two adjacent pins (default from differential I/O), wider width conversions of 10 and
14 bits can also be supported.
The ISERDES has a special oversampling mode capable of asynchronous data recovery for
applications like a 1.25 Gb/s LVDS I/O-based SGMII interface.
For more details on Select I/Os, see UG471
, 7 Series FPGAs SelectIO Resources User Guide.