User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 629
UG585 (v1.11) September 27, 2016
Chapter 21: Programmable Logic Description
21.3.3 GTX Low-Power Serial Transceivers
GTX low-power serial gigabit transceivers are available in the 7z030, 7z035, 7z045, and 7z100 devices
except where noted in the Serial Transceiver Channels by Device/Package table in UG865
, Zynq-7000
AP SoC Packaging Guide. The 7z030 has 0 or 4 GTX transceivers, the 7z035/7z045 has 8 or 16, and the
7z100 device has 16 GTX transceivers. Refer to the packaging guide to get the transceiver count for
each package type.
The 7z012s and 7z015 devices includes 4 GTP low-power serial transceivers. The GTP transceivers
are discussed in section 21.3.4 GTP Low-Power Serial Transceivers.
Some highlights of the GTX low-power gigabit transceivers include:
• High-performance transceivers capable of up to 12.5 Gb/s line rates with flipchip packages and
up to 6.6Gb/s with bare-die flipchip packages.
• Low-power mode optimized for chip-to-chip interfaces.
• Advanced Transmit pre and post emphasis, and receiver linear (CTLE) and decision feedback
equalization (DFE), including adaptive equalization for additional margin
Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the
backplane, or over longer distances is becoming increasingly popular and important to enable
customer line cards to scale to 200 Gb/s. It requires specialized dedicated on-chip circuitry and
differential I/O capable of coping with the signal integrity issues at these high data rates.
The Zynq-7000 AP SoC devices transceiver counts range from 0 to 16 transceiver circuits. Each serial
transceiver is a combined transmitter and receiver. The various Zynq-7000 serial transceivers can use
a combination of ring oscillators and LC tank architecture to allow the ideal blend of flexibility and
performance while enabling IP portability across the family members. Lower data rates can be
achieved using logic-based oversampling of PL. The serial transmitter and receiver are independent
circuits that use an advanced PLL architecture to multiply the reference frequency input by certain
programmable numbers between 4 and 25 to become the bit-serial data clock. Each transceiver has
a large number of user-definable features and parameters. All of these can be defined during device
configuration, and many can also be modified during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32,
40, 64, or 80. This allows the designer to trade-off datapath width for timing margin in
high-performance designs. These transmitter outputs drive the PC board with a single-channel
differential output signal. TXOUTCLK is the appropriately divided serial data clock and can be used
directly to register the parallel data coming from the internal logic. The incoming parallel data is fed
through an optional FIFO and has additional hardware support for the 8B/10B, 64B/66B, or 64B/67B
encoding schemes to provide a sufficient number of transitions. The bit-serial output signal drives
two package pins with differential signals. This output signal pair has programmable signal swing as
well as programmable pre- and post-emphasis to compensate for PC board losses and other
interconnect characteristics. For shorter channels, the swing can be reduced to reduce power
consumption.