User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 645
UG585 (v1.11) September 27, 2016
Chapter 21: Programmable Logic Description
21.3.5 Integrated I/O Block for PCIe
The integrated PCI Express I/O block is only supported in the 7z012s, 7z015, 7z030, 7z035, 7z045,
and 7z100 devices. Highlights of the integrated blocks for PCI Express include:
• Compatible with the PCI Express Base Specification 2.1 with Endpoint and Root Port capability
• Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s)
• Advanced configuration options, advanced error reporting (AER), and end-to-end CRC (ECRC)
advanced error reporting and ECRC features in the integrated block depending on family
All Zynq-7000 AP SoC devices with transceivers include an integrated block for PCI Express
technology that can be configured as an Endpoint or Root Port, compatible with the PCI Express Base
Specification Revision 2.1. The Root Port can be used to build the basis for a compatible Root
Complex, to allow custom communication between the Zynq-7000 AP SoC device and other devices
via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet controllers or
fibre channel HBAs, to the Zynq-7000 devices.
This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at
the 2.5 Gb/s and 5.0 Gb/s data rates. For high-performance applications, advanced buffering
techniques of the block offer a flexible maximum payload size of up to 1,024 bytes. The integrated
block interfaces to the integrated high-speed transceivers for serial connectivity and to block RAMs
for data buffering. Combined, these elements implement the physical layer, data link layer, and
transaction layer of the PCI Express protocol.
Xilinx provides a light-weight, configurable, easy-to-use LogiCORE™ IP wrapper that ties the various
building blocks (the integrated block for PCI Express, the transceivers, block RAM, and clocking
resources) into an Endpoint or Root Port solution. The system designer has control over many
configurable parameters: lane width, maximum payload size, programmable logic interface speeds,
reference clock frequency, and base address register decoding and filtering.
Xilinx offers AXI4 memory mapped wrapper for the integrated block. AXI4 (memory mapped) is
designed for Vivado/EDK design flow and MicroBlaze™ processor based designs.
For more details on PCIe, see UG477
, 7 Series FPGAs Integrated Block v1.3 for PCI Express User Guide.