User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 653
UG585 (v1.11) September 27, 2016
Chapter 22: Programmable Logic Design Guide
A few performance insights can be inferred from these relative throughputs.
• The OCM or DDR memories are not able to be fully utilized by a single master, except if a low
DDR clock rate is used. For example, DDR read bandwidth is limited to 2,840 MB/s on a
particular port by the memory interconnect.
• The interconnect generally provides enough bandwidth to sustain access to the memory
devices.
22.3.2 DDR Efficiency
One design consideration when using the PL to access external memory is the total amount of DDR
memory bandwidth that is available. One useful metric of DDR bandwidth is the efficiency of the
controller. Efficiency is the total data passed through the controller versus its theoretical throughput
during a test period. Table 22-5 and Table 22-6 lists the efficiency the DDR controller under various
access types. The system is configured according to Table 22-7.
From a design planning perspective, accesses tested in Table 22-5 could be described as optimistic
to near-typical values. The random read/write pattern is not worst case as the DDR controller
optimization features are still able to improve efficiency; there might be other more pessimistic
access patterns. Overall, the DDR controller was designed to have a maximum efficiency of
approximately 75%.
Table 22-6 lists a DDR efficiency versus burst length example. It illustrates that moderate length
bursts do not result in significant DDR efficiency loss. These moderate burst lengths can be useful in
latency-sensitive environments where longer bursts can increase latency for higher-priority masters
in the system.
Table 22-4: Theoretical Bandwidth of PS Interconnect
Interconnect
Clock
Domain
IF Width
(Bits)
IF Clock
(MHz)
Read BW
(MB/S)
Read BW
(MB/S)
R+W BW
(MB/s)
Central Interconnect CPU_2x 64 222 1,776 1,776 3,552
Masters CPU_1x 32 111 444 444 888
Slaves CPU_1x 32 111 444 444 888
Master Interconnect CPU_2x 32 222 888 888 1,776
Slave Interconnect CPU_2x 32 222 888 888 1,776
Memory Interconnect DDR_2x 64 355 2,840 2,840 5,680
Table 22-5: DDR Efficiency (System #1, 4 HP/AFI masters, AXI Burst Length of 16)
Access Type Address Pattern Efficiency (%)
Reads Sequential 97
Reads Random 92
Writes Sequential 90
Writes Random 87
Reads and Writes Sequential 87
Reads and Writes Random 79