User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 67
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
Cortex-A9 also employs an 8-entry return stack cache that holds the 32-bit subroutine return
addresses. This feature greatly reduces the penalty of executing subroutine calls and can address
nested routines up to eight levels deep.
Instruction and Data Alignment
ARM architecture specifies the ARM instructions as being 32-bits wide and requires them to be
word-aligned. Thumb instructions are 16-bits wide and are required to be half-word aligned.
Thumb-2 instructions which are 16- or 32-bits wide are also required to be half-word aligned. Data
accesses can be unaligned and the load/store unit within the CPU breaks them up to aligned
accesses. The data from these accesses are merged and sent to the register file within the CPU as had
been requested.
Note: The application processing unit (APU), and the PS as a whole, support only little-endian
architecture for both instruction and data.
Trace and Debug
The Cortex-A9 processor implements the ARMv7 debug architecture as described in the ARM
Architecture Reference Manual. In addition, the processor supports a set of Cortex-A9
processor-specific events and system-coherency events. For more information, see Chapter 11,
Performance Monitoring Unit in the ARM Cortex-A9 Technical Reference Manual.
The debug interface of the processor consists of:
• A baseline CP14 interface that implements the ARMv7 debug architecture and the set of debug
events as described in the ARM Architecture Reference Manual
• An extended CP14 interface that implements a set of debug events specific to this processor
(explained in the ARM Architecture Reference Manual)
• An external debug interface connected to an external debugger through a debug access port
(DAP)
The Cortex-A9 includes a program trace module that provides ARM CoreSight technology
compatible program-flow trace capabilities for either of the Cortex-A9 processors and provides full
visibility into the actual instruction flow of the processor. The Cortex-A9 PTM includes visibility over
all code branches and program flow changes with cycle-counting enabling profiling analysis. The
PTM block in conjunction with the CoreSight design kit provides the software developer the ability to
non-obtrusively trace the execution history of multiple processors and either store this, along with
time stamped correlation, into an on-chip buffer, or off chip through a standard trace interface so as
to have improved visibility during development and debug.
The Cortex-A9 processor also implements program counters and event monitors that can be
configured to gather statistics on the operation of the processor and the memory system.
3.2.3 Level 1 Caches
Each of the two Cortex-A9 processors has separate 32 KB level-1 instruction and data caches. Both L1
caches have common features that include: