User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 672
UG585 (v1.11) September 27, 2016
Chapter 24: Power Management
24.2.3 APU Maximum Frequency
For applications which do not require the maximum amount of processing performance, the APU
maximum frequency can be reduced to meet application needs. A lower clock frequency can
significantly reduce the operating power when compared to operating at a higher frequency
.
24.2.4 DDR Memory Clock Frequency
For applications which do not require the maximum amount of DDR bandwidth, the DDR bandwidth
can be reduced to meet application needs. This can reduce operating power significantly compared
operating at a higher frequency, but more importantly, allows the use of lower power DDR standards
and configurations.
24.2.5 DDR Memory Controller Modes and Configurations
The DDR2, DDR3, and LPDDR2 DDR standards are supported in both 16- and 32-bit data operation.
DDR power can be a significant percentage of total power, so minimizing DDR power is an important
means of reducing system power.
The following features impact DDR power:
• The highest power DDR standard is a DDR2 due to the 1.8V operating voltage and the
termination requirements.
• The highest speed DDR standard is DDR3 operating up to 1,066 Mb/s in -1 devices.
• The lowest power interface DDR standard is LPDDR2 due to the 1.2V operating voltage and the
unterminated I/Os, however rates are limited compared to DDR3.
• DDR width can be set to 16 or 32 bits. Note that, for ECC, use a 32-bit bus width (16-bit data,
10-bit ECC).
• The total number of DDR devices in the system impacts system power. For example, four 8-bit
DDR devices have a higher system power than two 16-bit devices.
• 32-bit DDR devices are available only for LPDDR2.
• Termination strength: If possible use the highest possible termination value. A termination value
of 40Ω is 50% more termination power than 60Ω.
24.2.6 Boot Interface Options
The PS supports boot from Quad-SPI, NAND, and NOR devices. Boot devices do not impact system
level dynamic power as the boot process only occurs once at device power up. Lower voltage 1.8V
devices are of lower static power than higher 3.3V devices.
24.2.7 PS Clock Gating
The PS supports many clock domains, each with independent clock gating control. When the system
is in run mode, the user is allowed to shut down the clock domains that are not used and reduce the
dynamic power dissipation.