User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 675
UG585 (v1.11) September 27, 2016
Chapter 24: Power Management
24.4 Sleep Mode
Sleep mode is defined at the system level to include the APU in standby mode and multiple
controllers being held in reset without a clock.
Going into sleep mode can greatly reduce power consumption. In sleep mode, most function clock
groups are turned off or powered off. The only required active devices are one CPU, the snoop
control unit (SCU), and a wake-up device. Ideally, the only devices causing dynamic power
consumption should be the SCU and the wake-up peripheral device. The wake-up device can be
UART, GPIO, or any device that can generate an interrupt.
If the wake-up device is an AXI bus master, which can start transactions targeting the DRAM,
additional limitations apply. Because the whole interconnect and the DDR memory are in low power
modes and inaccessible, it must be assured that the CPU goes through the full wake-up process
before any transactions to the DRAM take place. This guarantees that potential transactions
targeting the DRAM are served correctly.
24.4.1 Setup Wake-up Events
Every interrupt signaled to the PS can be used as a wake-up event. To make this happen, the wanted
interrupt must be enabled in the peripheral and the GIC. A wake-up device must be able to generate
the interrupt in sleep mode, which means, that its clocks might not be gated off. See GPIO as
Wake-up Event, page 388 for more information.
Refer to the respective chapter for information about available interrupts and how to configure the
peripherals to generate them.
24.4.2 Programming Guide
The following shows the preliminary steps to enter PS sleep mode from normal running mode and
exit from it. In sleep mode, the master CPU is responsible for shutting down all non-wake up devices,
including all other masters in the system and the PL, if possible. Since clock frequencies change when
clock dividers and PLL configurations are changed, configuring a wake-up device might not only
mean activating the wanted wake-up interrupt, but also changing the peripheral configuration to be
able to cope with the modified clock frequency. If both CPUs are running, the master CPU should
shut down the secondary CPU first before proceeding with the steps described below. It is user’s
choice, which CPU acts as master CPU. Furthermore, precautions must be taken to keep code which
is executed while the DDR clocks are disabled accessible in this period e.g., by placing those
code-segments in OCM, or locking the L2 cache and TLB. Depending on the actual implementation
this can, amongst others, apply to:
• Code executed when DDR is not available
• Routine for entering and exiting standby mode
•Translation table
•Stacks