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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 68
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• Each cache can be disabled independently, using the system control coprocessor. Refer to the
System Control Register in the ARM Cortex-A9 Technical Reference Manual.
• The cache line lengths for both L1 caches are 32 bytes.
• Both caches are 4-way set-associative.
• L1 caches support 4 KB, 64 KB, 1 MB, and 16 MB virtual memory page.
• Neither of the two L1 caches supports the lock-down feature.
• The L1 caches have 64-bit interfaces to the integer core and AXI master ports.
• Cache replacement policy is either pseudo round-robin or pseudo-random. The victim counter
is read at time of miss, not allocation, and it is incremented on allocation. An invalid line in the
set is replaced in preference to using the victim counter.
• On a cache miss, critical word first filling of the cache is performed.
• To reduce power consumption, the number of full cache reads is reduced by taking advantage of
the sequential nature of many cache operations. If a cache read is sequential to the previous
cache read, and the read is within the same cache line, only the data RAM set that was
previously read is accessed.
• Both L1 caches support parity.
• All memory attributes are exported to external memory systems.
• Support for TrustZone security exports the secure or non-secure status to the caches and
memory system.
• Upon a CPU reset, the contents of both L1 caches are cleared to comply with security
requirements.
Note: You must invalidate the instruction cache, the data cache, and BTAC before using them. It is
not required to invalidate the main TLB, even though it is recommended for safety reasons. This
ensures compatibility with future revisions of the processor.
The L1 instruction-side cache (I-Cache) is responsible for providing an instruction stream to the
Cortex-A9 processor. The L1 I-Cache interfaces directly to the pre-fetch unit which contains a
two-level prediction mechanism as described in the Branch Prediction section of this chapter. The L1
instruction cache is virtually indexed and physically tagged.
The L1 data-side cache (D-Cache) is responsible for holding the data used by the Cortex-A9
processor. Key features of the L1 D-Cache include:
• Data cache is physically indexed and physically tagged.
• D-Cache is non-blocking and, therefore, load/store instructions can continue to hit the cache
while it is performing allocations from external memory due to prior read/write misses. The data
cache supports four outstanding reads and four outstanding writes.
• The CPU can support up to four outstanding preload (PLD) instructions. However, explicit
load/store instructions have higher priority.
• The Cortex-A9 load/store unit supports speculative data pre-fetching which monitors sequential
accesses made by program and starts fetching the next expected line before it has been
requested. This feature is enabled in the cp15 Auxiliary Control register (DP bit). The
pre-fetched lines can be dropped before allocation, and PLD instruction has higher priority.
• The data cache supports two 32-byte line-fill buffers and one 32-byte eviction buffer.
• The Cortex-A9 CPU has a store buffer with four 64-bit slots with data merging capability.