User manual

Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 682
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
25.2 CPU Clock
Figure 25-3 shows the clock generation network in the CPU clock domains.
Ratio Examples
The CPU clock domain operates in two modes 6:2:1 and 4:2:1. Table 25-1 shows example frequencies
for these modes and modules operating in each clock domain. (See the applicable Zynq-7000 AP SoC
data sheet for the specific allowed frequencies for each clock.)
CPU Clock Divisor Restriction
To improve the quality of the high speed clocks going to the CPU and DDR, there is a requirement
that they get divided by an even number in the slcr.ARM_CLK_CTRL [DIVISOR] bit field. For the
slcr.ARM_CLK_CTRL [DIVISOR], software must program the following values: DIVISOR =2, =4, or >4.
X-Ref Target - Figure 25-3
Figure 25-3: CPU Clock Generation and Domains
UG585_c25_03_022912
ARM PLL
DDR PLL
IO PLL
[5][4]
6-bit
Programmable
Divider
[13:8]
ARM_CLK_CTRL
ARM_CLK_CTRL
ARM_CLK_CTRL [24]
CPU_6x4x
Glitch-
Free
Glitch-Free
Glitch-
Free
Glitch-
Free
1
0
1
0
1
Clock
Ratio
Generator
ARM_CLK_CTRL [25]
Closely Coupled,
Always 2:1 Ratio
CPU_3x2x
2:1
ARM_CLK_CTRL [26]
CPU_2x
2:1 or 3:1
ARM_CLK_CTRL [27]
Closely Coupled,
Always 2:1 Ratio
CPU_1x
6:1 or 4:1
CLK_621_TRUE [0]
Table 25-1: CPU Clock Frequency Ratio Examples
CPU Clock 6:2:1 4:2:1 Clock Domain Modules
CPU_6x4x 800 MHz
(6 times faster than CPU_1x)
600 MHz
(4 times faster than CPU_1x)
CPU clock frequency, SCU, and OCM
arbitration, NEON, L2 cache memory
CPU_3x2x 400 MHz
(3 times faster than CPU_1x)
300 MHz
(2 times faster than CPU_1x)
APU timers
CPU_2x 266 MHz
(2 times faster than CPU_1x)
300 MHz
(2 times faster than CPU_1x)
I/O peripherals, central interconnect,
master interconnect, slave interconnect,
and OCM RAM
CPU_1x 133 MHz 150 MHz I/O peripherals AHB and APB interface
busses