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Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 683
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
Clock Usage
During normal usage, most system clocks will be derived by taking the input clock PS_CLK, sending
it through the PLL, and finally dividing it down to be used within the PS. While the PS generates many
different clocks, as shown in Figure 25-1, there are three clock domains that have the largest
interaction and importance in the system: These are the DDR_3x domain, the DDR_2x domain, and
the CPU clock domain. The DDR_3x clock domain includes the DDR memory controller. The DDR_2x
domain is primarily used for the high performance AXI interfaces to the PL (AXI_HP{0:3}) and the
interconnect. The CPU clock domain controls the ARM processors along with many of the CPU
peripherals.
The CPU clock domain is composed of four separate clocks: CPU_6x4x, CPU_3x2x, CPU_2x, and
CPU_1x. These four clocks are named according to their frequencies, which are related by one of two
ratios: 6:3:2:1 or 4:2:2:1 (abbreviated 6:2:1 and 4:2:1). The operating clock ratio is determined by the
CLK_621_TRUE [0] bit value. In the 6:2:1 mode, the frequency of the CPU_6x4x clock is 6 times as fast
as the CPU_1x clock. Table 25-1, page 682 shows examples of how these clocks are related. Refer to
the applicable Zynq-7000 AP SoC data sheet for the maximum clock frequency of each clock domain.
All the CPU clocks are synchronous to each other; while the DDR clocks are independent of each
other and the CPU clocks. The I/O peripheral clocks, such as CAN reference clocks and SDIO
reference clocks, are all generated by a similar method, starting from the PS_CLK pin, through a PLL,
then a divider, and finally to the peripheral destination. Each peripheral clock is completely
asynchronous to all other clocks.
Interconnect Clock Domains
The individual clock domains are shown in Figure 25-2. The central interconnect has two main clock
domains: the DDR_2x and the CPU_2x. For the five sub-switches, four clocks are in the CPU_2x clock
domain, while the memory interconnect clock is in the DDR_2x clock domain. The direct path
between the CPU (via the L2 cache) and DDR controller is in the DDR_3x clock domain, ensuring
maximum throughput.The direct path between CPU and OCM is in the CPU_6x4x clock domain. The
direct path between the SCU ACP and the PL is in the CPU_6x4x clock domain (clock domain crossing
between the PL clock domain and the CPU clock domain is done in an asynchronous AXI bridge in
the PS.
CPU Clock Stop
Each CPU clock can be individually stopped using slcr.A9_CPU_RST_CTRL.A9_CLKSTOP{0,1}.
PS Peripheral AMBA Clocks
Every peripheral within the PS is supplied with its own independently gated version of the CPU clock
for its AMBA bus connection to the control and status registers and sometimes to the controller logic
itself. This clock can be disabled when it is guaranteed that the peripheral is not addressed. This
gating is applied with a glitch-free clock gate as shown in Table 25-2.