User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 684
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
System Performance
The clock frequencies of the different clock domains of the PS help dictate total system performance.
In many cases, the highest frequency CPU clock results in the highest performance. However, some
users will find that the CPU is not the critical performer in the system and that bandwidth across the
interconnect is the bottleneck. In that case, it might be useful to switch the ratio from 6:2:1 to 4:2:1
mode. Depending on the device speed grade, the frequency of the CPU clocks might be limited by
the cpu_6x while in 6:2:1 mode and might be limited by the cpu_2x clock while in 4:2:1 mode.
Therefore, it is suggested that for those applications that might exchange some CPU performance
for interconnect performance, check the appropriate data sheet to determine the optimal
frequencies.
25.3 System-wide Clock Frequency Examples
There are two clock configuration examples for 6:2:1 mode in Table 25-3. The first example is when
the input PS_ CLK is at 33.33 MHz and the second example is when the input frequency is at 50 MHz.
Table 25-2: PS Peripheral Clock Control
AMBA Bus
Peripheral
Base Clock
Control Bits in APER_CLK_CTRL
0: Disable
1: Enable
DMAC CPU_2x DMA_CPU_2XCLKACT [0]
USB 0 CPU_1x USB0_CPU_1XCLKACT [2]
USB 1 CPU_1x USB1_CPU_1XCLKACT [3]
GigE 0 CPU_1x GEM0_CPU_1XCLKACT [6]
GigE 1 CPU_1x GEM1_CPU_1XCLKACT [7]
SDIO 0 CPU_1x SDI0_CPU_1XCLKACT [10]
SDIO 1 CPU_1x SDI1_CPU_1XCLKACT [11]
SPI 0 CPU_1x SPI0_CPU_1XCLKACT [14]
SPI 1 CPU_1x SPI1_CPU_1XCLKACT [15]
CAN 0 CPU_1x CAN0_CPU_1XCLKACT [16]
CAN 1 CPU_1x CAN1_CPU_1XCLKACT [17]
I2C 0 CPU_1x I2C0_CPU_1XCLKACT [18]
I2C 1 CPU_1x I2C1_CPU_1XCLKACT [19]
UART 0 CPU_1x UART0_CPU_1XCLKACT [20]
UART 1 CPU_1x UART1_CPU_1XCLKACT [21]
GPIO CPU_1x GPIO_CPU_1XCLKACT [22]
Quad-SPI CPU_1x LQSPI_CPU_1XCLKACT [23]
SMC CPU_1x SMC_CPU_1XCLKACT [24]