User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 689
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
25.6.2 Ethernet Clocks
The Ethernet Clocks generation network is shown in Figure 25-7.
Ethernet Receiver Clocks
There are two Ethernet receiver clocks. In normal functional mode, these are either sourced from an
external Ethernet PHY via the MIO or an extended MIO (EMIO). For MAC internal loopback mode,
these clocks are sourced from the internal Ethernet reference clocks. They are also gated with an
enable that can be used for power saving control. These are used to clock the receiver side of the
Gigabit Ethernet MAC IP.
The source selection multiplexer and the loopback selection multiplexer are not glitch free because
the source clocks might not be present. It is recommended that the clock be disabled before the
multiplexers are changed. To support loopback mode, enet0_rx_clk and enet1_rx_clk are supplied
with enet0_ref_clk and enet1_ref_clk.
Ethernet Transmit Clocks
Two Ethernet clocks are required to be generated: enet0_tx_clk and enet1_tx_clk. These are used to
clock the transmit side of the Ethernet MACs and as a source synchronous output clock for the RGMII
X-Ref Target - Figure 25-7
Figure 25-7: Ethernet Clock Generation
ARM PLL
DDR PLL
I/O PLL
6-bit
Programmable
Divider 0
GEM{0,1}_CLK_CTRL
ENET{0,1}_REF_CLK
6-bit
Programmable
Divider 1
1
0
1
0
MIO_ENET{0,1}_RX_CLK
ENET{0,1}_RX_CLK
Clock
Gate
NET_CTRL
[LOOPBACK_LOCAL, 1]
EMIO_ENET{0,1}_RX_CLK
Ethernet
Controller
(Rx)
[5]
[6]
1
0
1
0
ENET{0,1}_TX_CLK
Clock
Gate
EMIO_ENET{0,1}_TX_CLK
(signal from PL)
1
0
Ethernet
Controller
(Tx)
Glitch-
Free
[25:20][13:8]
[4]
[0]
GEM{0,1}_CLK_CTRL
GEM{0,1}_RCLK_CTRL
[0][4]
Not
Glitch-Free
Not
Glitch-Free
UG585_C25_07_022912
Not
Glitch-Free
Glitch-
Free
Glitch-Free
Glitch-Free
Glitch-Free
Glitch-Free