User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 690
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
interface. They are also used to provide a stable reference clock to the Ethernet receive paths when
internal loopback mode is selected.
These clocks can also be sourced from the EMIO. In this case, the associated RGMII interface is
disabled and the MAC connects to the PL through an MII or GMII interface. In this case, the Ethernet
reference clock must be provided by the PL. This is regardless of MII or GMII, where normally tx_clk
is an input in MII and an output in GMII.
When operating in MII or GMII mode, its reference clock is provided by the PL through the
eth*_emio_tx_clk. The EMIO source multiplexer is not glitch free because the EMIO source clock
cannot be relied upon to be present. It is anticipated that this source selection is a static
configuration or that the generated clock be gated before changing to the EMIO source. To support
loopback mode, gem0_rx_clk and gem1_rx_clk are supplied with gem0_ref_clk and gem1_ref_clk.
25.6.3 SDIO, SMC, SPI, Quad-SPI and UART Clocks
The SDIO, SMC, Quad SPI, and UART peripheral clocks all have the same programming model (see
Figure 25-8. The PLL source and divider values are shared for each I/O peripheral controller. The
clocks for each SDIO, SPI and the UART controller can be individually enabled/disabled. There is a
single clock, each, for the SMC and Quad SPI controllers.
The Quad-SPI clock is divided down by at least two using the Quad-SPI baud rate divider, see section
12.4.1 Clocks. In master mode, the SPI clock is divided down by at least four using the SPI baud rate
divider, see section 17.4.2 Clocks.
X-Ref Target - Figure 25-8
Figure 25-8: SDIO, SMC, SPI, Quad SPI and UART Reference Clocks
UG585_c25_08_0725712
I/O PLL
ARM PLL
DDR PLL
Clock
Gate
I/O Peripheral
Reference
Clocks
Glitch-Free
6-bit
Programmable
Divider
Glitch-Free
Divider Ctrl FieldMux Ctrl FieldMux Ctrl FieldControl RegisterI/O Peripheral Clock Enable Field
DevC
SMC
DIVISOR, 13:8SRCSEL, 5SRCSEL, 4SDIO_CLK_CTRL
DIVISOR, 13:8SRCSEL, 5SRCSEL, 4SMC_CLK_CTRL
SDIO 0
SDIO 1
CLKACT0, 0
CLKACT1, 1
DIVISOR, 13:8SRCSEL, 5SRCSEL, 4SPI_CLK_CTRL
SPI 0
SPI 1
CLKACT0, 0
CLKACT1, 1
CLKACT, 0
Quad-SPI
DIVISOR, 13:8SRCSEL, 5SRCSEL, 4LQSPI_CLK_CTRL
DIVISOR, 13:8SRCSEL, 5SRCSEL, 4UART_CLK_CTRL
UART 0
UART 1
CLKACT0, 0
CLKACT1, 1
CLKACT, 0
SDIO0_REF_CLK
SDIO
SMC
SPI
Quad SPI
UART
Glitch-
Free
0
1
SDIO1_REF_CLK
SMC_REF_CLK
SPI0_REF_CLK
SPI1_REF_CLK
QSPI_REF_CLK
UART0_REF_CLK
UART1_REF_CLK
Glitch-
Free
0
1