User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 696
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
25.10 Programming Model
25.10.1 Branch Clock Generator
Each clock generator has a clock control register <module>_CLK_CTRL. Within the clock control
register, the SRCSEL field selects a clock source and the DIVISOR field is the amount the source clock
is divided down to produce the desired clock frequency. Some clock generators have two cascaded
dividers.
To prevent the clock generator from exceeding the maximum frequency of the attached subsystem,
program the SRCSEL and the DIVISOR values in three separate steps:
1. Increase the value of the DIVISOR, as needed, so that the two PLL clock sources will not cause the
clock generator to exceed the maximum clock frequency of the subsystem.
2. Set the SRCSEL to the desired source.
CLK_621_TRUE Select CPU clock frequency ratio 6:2:1 or 4:2:1
DDR_CLK_CTRL DDR clock control
APER_CLK_CTRL AMBA peripheral clock control
TOPSW_CLK_CTRL Top-level switch clock control
PL Clocks
FPGA{3:0}_CLK_CTRL PS to PL output clock control
FPGA{3:0}_THR_{CTRL, CNT, STA} PS to PL output clock throttle
control, count and status
I/O Peripheral Clocks
GEM{1, 0}_RCLK_CTRL Gigabit Ethernet Rx clock control
• DIVISOR bit field (one or two parameters,
depending on the peripheral)
• Clock enable active control
GEM{1, 0}_CLK_CTRL Gigabit Ethernet ref clock control
SMC_CLK_CTRL SMC ref clock control
LQSPI_CLK_CTRL Quad-SPI ref clock control
SDIO_CLK_CTRL SDIO ref clock control
UART_CLK_CTRL UART ref clock control
SPI_CLK_CTRL SPI ref clock control
CAN_CLK_CTRL CAN ref clock control
CAN_MIOCLK_CTRL CAN comm port clock control
System Debug Clocks
DBG_CLK_CTRL CoreSight SoC trace clk control
PCAP_CLK_CTRL PCAP clock control This controls the frequency and enable of the
PCAP_2X clock for the DevC module.
Table 25-5: Clock Generation Register Overview (Cont’d)
Register Description Comments