User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 697
UG585 (v1.11) September 27, 2016
Chapter 25: Clocks
3. Update the DIVISOR to the desired value.
6-bit Programmable Divider
The 6-bit divider provides a divide range of 1 to 63, supports both even and odd divide values while
producing a close to 50% duty cycle, and is glitchless (divide values can be modified dynamically).
The only two exceptions to this rule are that the DDR_3X divider can only be programmed to divide
by an even divisor and the ARM_CLK_CTRL[DIVISOR] can not be programmed with a 1 or 3 when the
PLL is being used. Some reference clocks have one divider and some have two dividers.
25.10.2 DDR Clocks
IMPORTANT: It is a requirement that the DDR_3x clock must always be programmed to an even divisor.
RECOMMENDED: Changing the divider frequency does not produce glitches on the clock, however the
DDR controller will not necessarily operate correctly if the frequency is changed without modifying its
timing parameters. Therefore, it is suggested to first idle the DDR controller when the DDR clock is to
be reprogrammed.
25.10.3 Digitally Controlled Impedance (DCI) Clock
The digitally controlled impedance (DCI) clock is required by the DDR PHY for calibration. The DCI
clock is a low frequency clock, normally set to 10 MHz.
25.10.4 PLLs
The three PLLs share the clock input signal, PS_ CLK. Each PLL can be bypassed individually under
software control. As part of the power-on reset sequence, all PLLs can be bypassed using the
pll_bypass boot mode pin straps. (Refer to the boot mode section of Chapter 6, Boot and
Configuration.)
The PLL configuration and control registers are in the SLCR. The PLL frequency control registers
include the M (feedback divide ratio also known as PLL_FDIV), LOCK_CNT, PLL_CP, and PLL_RES
control fields. For each divide ratio M, the PLL_CP, PLL_RES, and LOCK_CNT fields must always be
written with the values shown in Table 25-6; the reset default values are not supported. After being
enabled, the PLL with take some time to lock. The length of time is specified by the tLOCK_PSPLL
data sheet parameter.
Enable PLL Mode when PLL Bypass Mode Pin is Tied High
After the system boots in bypass mode, the following sequence can be used to enable a PLL. Each
PLL can be individually enabled. This example shows how to enable the ARM PLL:
1. Program the ARM_PLL CTRL[PLL_FDIV] value and the PLL configuration register,
ARM_PLL_CFG[LOCK_CNT, PLL_CP, PLL_RES], to their required values.