User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 704
UG585 (v1.11) September 27, 2016
Chapter 26: Reset System
It does not filter Low-going glitches when the signal is intended to be held high. Any Low-going
glitch that is detected causes an immediate reset of the device.
The PS_POR_B signal is often connected to the power-good signal from the power supply. When
PS_POR_B is de-asserted, the system samples the boot strap mode pins and begins its internal
initialization process.
26.2.2 External System Reset (PS_SRST_B)
Power-on reset erases all debug configurations. The external system reset allows the user to reset all
of the functional logic within the device without disturbing the debug environment. For example, the
previous break points set by the user remain valid after the external system reset. While PS_SRST_B
is held Low, all PS I/Os are held in 3-state.
Due to security concerns, system reset erases all memory content within the PS, including the OCM.
The PL is also reset in system reset. System reset does not re-sample the boot mode strapping pins.
If this pin is not used in the system, it should be tied high.
26.2.3 System Software Reset
The user can reset the entire system by asserting a software reset. By asserting
PSS_RST_CTRL[SOFT_RST], the entire system is reset with the same end result as the user pressing the
PS_SRST_B pin (other than the REBOOT_STATUS register value being different).
Just like the other system resets, all of the RAMs are cleared and the PL is reset as well.
26.2.4 Watchdog Timer Resets
The watchdog timer resets are internally generated by the watchdog timers when they are enabled
and the timer expires. There are three different watchdog timers in the PS: one system-level timer
(SWDT) and one private timer in each of the two ARM cores (AWDT0 and AWDT1). The system-level
timer reset signal always resets the entire system, while the private watchdog timers can either reset
just the ARM core where it is housed, or the entire system.
26.2.5 Secure Violation Lock Down
When a security violation is detected, the entire PS is reset and locked down. After a security lock
down occurs, the PS only becomes active again by asserting and de-asserting the PS_POR_B reset
pin. Refer to Chapter 32, Device Secure Boot for details of how and when this signal is asserted.
26.2.6 Debug Resets
There are two types of debug resets that originate from the debug access port (DAP) controller;
debug system reset and debug reset.