User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 709
UG585 (v1.11) September 27, 2016
Chapter 27
JTAG and DAP Subsystem
27.1 Introduction
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1)
debug interface. Internally, the AP SoC device implements both an ARM debug access port (DAP)
inside the Processing System (PS) as well as a standard JTAG test access port (TAP) controller inside
the Programmable Logic (PL). The ARM DAP as part of ARM CoreSight debug architecture allows the
user to leverage industry standard third-party debug tools.
In addition to the standard JTAG functionality, the Xilinx TAP controller supports a number of PL
features including PL Debug, eFuse/BBRAM programming, on-chip XADC access, etc. Most
importantly, it also allows debugging of ARM software through the DAP and PL hardware by using
the TAP simultaneously with a trace buffer and cross triggering interface between the PS and PL.
Another important debug feature the Zynq-7000 AP SoC includes is debug trace support. This
feature allows the user to capture both the PS and PL trace into a common trace buffer that is either
read out through JTAG, described below, or sent out through the trace port interface unit (TPIU),
described in Chapter 28, System Test and Debug.
27.1.1 Block Diagram
Figure 27-1 shows the top level DAP/TAP architecture. As soon as the BootROM passes control to
user software, the JTAG chain is enabled automatically, assuming a non-secure boot process. This
allows debugging from the user software entry point.
JTAG supports two different modes: cascaded JTAG mode (also referred to as single chain mode) and
independent JTAG mode (also referred to as split chain mode). The mode is determined through the
mode input when the system comes out of reset.
In cascaded JTAG chain mode, both the TAP and DAP are visible from external JTAG debug tools or a
JTAG tester. With dedicated PL_TDO/TMS/TCK/TDI I/O at the PL side, only one JTAG cable can be
connected, though it has access both to PS and PL features concurrently.
To debug ARM software and the PL design simultaneously with separate cables, the user must switch
to independent JTAG mode. In this mode, JTAG cables only see the Xilinx TAP controller from the
dedicated PL_TDO/TMS/TCK/TDI pins. To debug ARM software, the user can route the ARM DAP
signals (PJTAG) through the MIO or through the EMIO and to PL SelectIO pins.
It is important to note that both the PS and PL must be powered on to use JTAG debug. Due to
security reasons, the JTAG chain is protected with triple redundancy gating logic to prevent