User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 71
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• Unaligned accesses can be performed.
• Multiple accesses can be merged by processor hardware into a smaller number of accesses of a
larger size. Multiple byte writes could be merged into a single double-word write, for example.
Memory Attributes
In addition to memory types, the ordering of accesses for regions of memory is also defined by the
memory attributes. The following sub-sections discuss these attributes.
Shareability
Shareability domains define zones within the bus topology within which memory accesses are to be
kept consistent (taking place in a predictable way) and potentially coherent (with hardware support).
Outside of this domain, masters might not see the same order of memory accesses as inside it. The
order of memory accesses takes place in these defined domains. Table 3-1 shows the different
shareability options available in a Cortex-A9 system:
Shareability only applies to normal memory, and to device memory in an implementation that does
not include the large physical address extensions (LPAE). In an implementation that includes the
LPAE, device memory is always outer shareable. For more information on LPAE, refer to the ARM
Technical Reference Manual.
Cacheability
Cacheable attributes apply only for the normal memory type. These attributes provide a mechanism
of coherency control with masters that lie outside the shareability domain of a region of memory.
Each region of normal memory is assigned a cacheable attribute that is one of:
• Write-back cacheable
• Write-through cacheable
• Non-cacheable
Table 3-1: Shareability Domains
Domain Abbreviation Description
Non-Shareable NSH A domain consisting only of the local master. Accesses that never need to
be synchronized with other cores, processors or devices. Not normally
used in SMP systems.
Inner shareable ISH A domain (potentially) shared by multiple masters, but usually not all
masters in the system. A system can have multiple inner shareable
domains. An operation that affects one inner shareable domain does not
affect other inner shareable domains in the system.
Outer shareable OSH A domain almost certainly shared by multiple masters, and quite likely
consisting of several inner shareable domains. An operation that affects an
outer shareable domain also implicitly affects all inner shareable domains
within it.
Full system SY An operation on the full system affects all masters in the system; all
non-shareable regions, all inner shareable regions and all outer shareable
regions.