User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 712
UG585 (v1.11) September 27, 2016
Chapter 27: JTAG and DAP Subsystem
27.2 Functional Description
Figure 27-3 shows the ARM DAP and JTAG TAP controllers connected in daisy-chain order with the
ARM DAP at the front of chain. The two JTAG controllers belong to two different power domains. The
ARM DAP is in the PS power domain while the TAP is in the PL power domain. JTAG I/O pads are
located in the PL power domain to take advantage of existing JTAG I/O pads in the PL. Although the
PS supports PL power down mode, both power domains must be powered on to support all JTAG
related features.
The ARM DAP controller has a 4-bit IR length and the TAP controller has a 6-bit IR length. The two
controllers operate completely independently. The user can access the TAP and ARM DAP controller
simultaneously in independent mode. Due to security reasons, the ARM DAP controller is bypassed
when the PS is out of reset. The Xilinx TAP controller within the PL can be disabled through the eFuse
or the control register within the PL configuration logic.
All debug components within the PS are under direct control of the debug tools, such as ARM RVDS
or Xilinx XDK, through ARM DAP. All debug components (including DAP) within the PS are designed
and integrated following ARM CoreSight architecture. Although there is no CoreSight component
within the PL, FTM components within the PS allows a PL trace to be dumped into the ETB. CTI/CTM
supports cross triggering between the PS and PL.
As shown in Figure 27-3, all PS debug components are tied to the debug APB bus with the DAP as the
only bus master. External debug tools connected to the ARM DAP through JTAG uses the debug APB
bus to configure all debug components including CPU, CTI/CTM, PTM, ITM, and FTM. Debug APB is
also used to extract trace data from the ETB. It is a complicated process to configure all of the debug
components properly to support user debug needs. Fortunately, most of the work is automatically
handled by the debug tools. However, understanding Zynq debug architecture is necessary to better
utilize the full system debug capability.
Other than debug control, the ARM DAP also acts as master device within the system interconnect.
In previous debug systems, it was required to halt the CPU in order to probe system address space.
This new arrangement allows the user to access system address space without halting the CPU. (See
Chapter 28, System Test and Debug for more information).