User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 713
UG585 (v1.11) September 27, 2016
Chapter 27: JTAG and DAP Subsystem
The PL Xilinx TAP controller serves four key purposes: boundary scan test, eFuse programming,
BBRAM programming, and PL debug chipscope.
The TPIU provides the mechanism to capture trace over long periods of time. There is no internal
time limit to how long a trace can be dumped so the only practical limit is the Zynq-7000 bandwidth.
If doing a trace dump using PS I/O through MIO, the maximum trace bandwidth depends on how
many MIO trace I/Os could be allocated. Another alternative is trace dump through EMIO. PL soft
logic connects the EMIO trace signal to the PL SelectIO. There are other potential innovative ways to
handle EMIO trace.
For example, users could loopback EMIO trace data back to the PS and store it in DDR memory or
export trace via gigabit Ethernet to enable remote debug or monitor. In typical debug flow, the user
enables minimum trace source dumping capability to fit trace data into allocated TPIU throughput.
After a small time window when debug occurs as determined through trace monitoring, the user
could enable full trace dumping capability if required, and store short periods of data into the ETB
for the next level of debug. Other than debugging, trace port also brings significant value for
software profiling. Soft profiling helps the user to identify those software routines that consume the
X-Ref Target - Figure 27-3
Figure 27-3: Debug System Architecture
PL Logic
CTM
ITM
Funnel
(CSTF)
TPIU
4K
ETB
Trace Port
Top Switch
AHB-
AXI
Debug JTAG Interface
(Chipscope)
PL
XILINX TAP
JTAG-DP
ARM DAP
PS_Pad
PL_Pad
TDO
TDI TDO
TDI
Xilinx Custom Design
Debug APB
FTM
Trace
TDI
TDO
PS
Trace ATB
AHB-AP
CTI
CPU
PTM
CPU
PTM
CTI
APB-AP
CTI
CTI
CTM
Time Stamp
Time Stamp
Cross Triggering
Trace Bus(ATB)
Debug APB
CPU Debug
ROM
eFuse BBRAM
UG585_c27_03_021313
Cross Trig(8)