User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 739
UG585 (v1.11) September 27, 2016
Chapter 29: On-Chip Memory (OCM)
• The RAM array is 128-bits wide.
• The OCM switch port has separate read and write channels that can be simultaneously active.
• The SCU (CPU/ACP) port has separate read and write channels that can be simultaneously
active.
• The SCU (CPU/ACP) port channels have a fixed arbitration priority higher than the OCM switch
port by default.
As a result of these constraints, saturation of the RAM can occur by the SCU CPUs or ACP interfaces,
starving the OCM switch and the masters it serves. However, if the CPU(s) are running with caches on,
the rate at which they produce new commands to this module is sufficiently low to allow the OCM
switch port to share the RAM. The arbitration priority of the OCM switch can also be raised above the
priority of the SCU write channels.
Configuring OCM memory as Device Memory in the MMU or using narrow, non-modifiable accesses
through the ACP can also contribute to OCM switch port starvation; see section 29.2.2 Optimal
Transfer Alignment.
In general, the guidelines of ACP usage detailed under the ACP chapter should be followed, as this
port effectively produces commands on the SCU port to the OCM, which might cause starvation to
the OCM switch.
29.2.5 Address Mapping
The address range assigned to the OCM can be modified to exist in the first or last 256 KB of the
address map, to flexibly handle the ARM low or high exception vector modes. In addition, the CPU
and ACP AXI interfaces can have their lowest 1 MB address range accesses diverted to DDR, using
the SCU address filtering feature. This section describes these features through a series of example
address configurations.
Mapping Summary
(See Appendix B, Register Details for detailed register information.)
When addressing the OCM the following details should be considered:
• The 256 KB RAM array can be mapped to either a low address range (0x0000_0000 to
0x0003_FFFF) or a high address range (0xFFFC_0000 to 0xFFFF_FFFF) in a granularity of
four independent 64 KB sections via the 4-bit slcr.OCM_CFG[RAM_HI].
• The SCU address filtering (mpcore.SCU_CONTROL_REGISTER[Address_filtering_enable]) field is
set by hardware on any form of reset and should not be disabled by the user. Address filtering
on non-OCM addresses is necessary to correctly route transactions between the two
downstream SCU ports.The address filtering range has a 1 MB granularity.
• The SCU address filtering feature is able to redirect accesses from its CPU and ACP masters
targeting the range (0x0000_0000 to 0x000F_FFFF) which includes the OCM's low address
range, to the PS DDR DRAM, independent of the RAM address settings.
• For each 64 KB section mapped to the high OCM address range via slcr.OCM_CFG[RAM_HI]
which is not also part of the SCU address filtering range will be aliased for CPU and ACP masters
at a range of 0x000C_0000-0x000F_FFFF.