User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 74
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
• Memory types: strongly-ordered, device, or normal
• Shareability
• Cacheability
The following rules apply when a physical memory location is accessed with mismatched attributes:
1. When a memory location is accessed with mismatched attributes, the only software visible
effects are one or more of the following:
°
Uni-processor semantics for reads and writes to that memory location might be lost. This
means:
- A read of the memory location by a thread of execution might not return the value most
recently written to that memory location by that thread of execution.
- Multiple writes to a memory location by a thread of execution which uses different
memory attributes might not be ordered in program order.
°
There might be a loss of coherency when multiple threads of execution attempt to access a
memory location.
°
There might be a loss of properties derived from the memory type.
2. If the mismatched attributes for a location mean that multiple cacheable accesses to the location
might be made with different shareability attributes, then coherency is guaranteed only if each
thread of execution that accesses the location with a cacheable attribute performs a clean and
invalidate of the location.
3. The possible loss of properties caused by mismatched attributes for a memory location are
defined more precisely if all of the mismatched attributes define the memory location as one of:
°
Strongly-ordered memory
°
Device memory
°
Normal inner non-cacheable, outer non-cacheable memory
In these cases, the only possible software-visible effects of the mismatched attributes are one or
more of:
°
A possible loss of properties derived from the memory type when multiple threads of
execution attempt to access the memory location
°
A possible re-ordering of memory transactions to the memory location that use different
memory attributes, potentially leading to a loss of coherency or uni-processor semantics.
Any possible loss of coherency or uniprocessor semantics can be avoided by inserting DMB
barrier instructions between accesses to the same memory location that might use different
attributes.
4. If the mismatched attributes for a memory location all assign the same shareability attribute to
the location, any loss of coherency within a shareability domain can be avoided. To do so,
software must use the techniques that are required for the software management of the
coherency of cacheable locations between threads of execution in different shareability domains.
This means:
°
If any thread of execution might have written to the location with the write-back attribute,
before writing to the location not using the write-back attribute, a thread of execution must
invalidate, or clean, the location from the caches. This avoids the possibility of overwriting
the location with stale data.