User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 745
UG585 (v1.11) September 27, 2016
Chapter 30
XADC Interface
30.1 Introduction
The Xilinx analog mixed signal module, referred to as the XADC, is a hard macro. It has JTAG and
DRP interfaces for accessing the XADC’s status and control registers in the 7-series FPGAs.
Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to
control the XADC. The Zynq-7000 AP SoC devices combine a flexible analog-to-digital converter with
programmable logic to address a broad range of analog data acquisition and monitoring
requirements. The XADC is part of a larger analog mixed signal (AMS) topic that is a combination of
analog and digital circuits.
The XADC has two 12-bit 1 mega samples per second (MSPS) ADCs with separate track and hold
amplif
iers, an analog multiplexer (up to 17 external analog input channels), and on-chip thermal and
on-chip voltage sensors. The two ADCs can be
conf
igured to simultaneously sample two
external-input analog channels. The track and hold
amplif
iers support a range of analog input signal
types, including unipolar, bipolar, and differential. The analog inputs can support signal bandwidth
of 500 KHz at sample rate of 1 MSPS. An external analog multiplexer can be used to increase the
number of external channels supported without the cost of additional package pins.
The XADC optionally uses an on-chip reference circuit, thereby eliminating the need for external
active components for basic on-chip monitoring of temperature and power supply rails. To achieve
the full 12-bit performance of the ADCs, an external 1.25V reference IC is recommended.
The most recent measurement results (together with maximum and minimum readings) are stored in
dedicated registers.
User-def
ined alarm thresholds can automatically indicate over-temperature
events and unacceptable power supply variation. A
user
-
specif
ied limit (for example, 100°C) can be
used to initiate a software-controlled system power-down.
Control Interfaces
Software running in the PS can communicate with the XADC in one of two ways:
• PS-XADC Interface: a 32-bit APB slave interface on the PS interconnect that is FIFO’d and
serialized.
• PS to PL AXI master could also be used to control the XADC via the AXI XADC core logic.
Development tools can connect to the PL-JTAG pins and control many parts of the AP SoC including
the XADC. The interface is described in Chapter 27, JTAG and DAP Subsystem. The PL-JTAG interface
and the internal PS-XADC interface cannot be used at the same time. The selection between the