User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 75
UG585 (v1.11) September 27, 2016
Chapter 3: Application Processing Unit
°
After writing to the location with the write-back attribute, a thread of execution must clean
the location from the caches to make the write visible to external memory.
°
Before reading the location with a cacheable attribute, a thread of execution must invalidate
the location from the caches to ensure that any value held in the caches reflects the last
value made visible in external memory.
In all cases:
°
Location refers to any byte within the current coherency granule.
°
A clean and invalidate operation can be used instead of a clean operation, or instead of an
invalidate operation.
°
To ensure coherency, all cache maintenance and memory transactions must be completed,
or ordered by the use of barrier operations.
5. If all aliases of a memory location that permit write access to the location assign the same
shareability and cacheability attributes to that location, and all these aliases use a definition of
the shareability attribute that includes all the threads of execution that can access the location,
then any thread of execution that reads the memory location using these shareability and
cacheability attributes accesses it coherently, to the extent required by that common definition
of the memory attributes.
3.2.5 Memory Management Unit (MMU)
The MMU in the ARM architecture involves both memory protection and address translation. The
MMU works closely with the L1 and L2 memory systems in the process of translating virtual
addresses to physical addresses. It also controls accesses to and from the external memory.
The MMU is compatible with the Virtual Memory System Architecture version 7 (VMSAv7)
requirements supporting 4 KB, 64 KB, 1 MB, and 16 MB page table entries and 16 access domains.
The unit provides global and application-specific identifiers to remove the requirement for context
switch TLB flushes and has the capability for extended permission checks. Please see the ARM
Architecture Reference Manual for a full architectural description of the VMSAv7.
The processor implements the ARMv7-A MMU enhanced with security extensions and
multiprocessor extensions to provide address translation and access permission checks. The MMU
controls table-walk hardware that accesses translation tables in main memory. The MMU enables
fine-grained memory system control through a set of virtual-to-physical address mappings and
memory attributes held in instruction and data translation look-aside buffers (TLBs).
In summary, the MMU is responsible for the following operations:
• Checking of virtual address and ASID (address space identifier)
• Checking of domain access permissions
•Checking of memory attributes
• Virtual-to-physical address translation
• Support for four page (region) sizes
• Mapping of accesses to cache, or external memory
• Four entries in the main TLB are lockable