User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 751
UG585 (v1.11) September 27, 2016
Chapter 30: XADC Interface
30.2.2 Serial Communication Channel (PL-JTAG and PS-XADC)
The serial communication channel connects the XADC to the PS-XADC or PL-JTAG interface,
depending on the devcfg.XADCIF_CFG [ENABLE] bit setting.
The channel is a full duplex synchronous bit-serial link with dedicated control signals using a JTAG
protocol. By default, after reset, the connection between the PS and XADC (PS-XADC interface) is
disabled. PS software can write a
1
to the devcfg.XADCIF_CFG [ENABLE] bit to control the source
and switch the communication channel from the PL-JTAG interface to the PS-XADC interface. When
the PS-XADC interface is enabled to control the XADC, the XADC is no longer accessible by the
PL-JTAG interface. The inverse is true, when XADC is accessible by PL-JTAG, it can not be accessed by
the PS-XADC.
The PS-XADC interface interacts with the PS via an APB 3.0 interface on the PS interconnect. This
interface is part of the DevC module and is described in section 6.4 Device Boot and PL
Configuration.
30.2.3 Analog-to-Digital Converter (All)
The functions and features of the XADC are described in UG480, 7 Series FPGAs and Zynq-7000 All
Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.
30.2.4 Sensor Alarms (PS-XADC and DRP)
The XADC can generate an alarm signal when an internal sensor measurement exceeds the value
programmed into the XADC threshold register. The alarm thresholds are stored in the XADC Control
registers, refer to UG480
for their descriptions.
PS-XADC Interface
The alarm signals are routed directly from the XADC block into the PS_XADC interface block, thus
allowing alarm status to be reflected directly in the PS XADC’s interface registers and enabling alarms
to trigger interrupts.
Individual alarm interrupts can be disabled using the devcfg.XADCIF_INT_MASK register.
The alarm signals are sent to the PS-XADC Interface Status register. This register is masked and the
masked interrupts are OR’d together to generate the IRQ ID #39 interrupt to the PS interrupt
controller.
When an alarm goes active, it triggers a maskable interrupt. The alarm signals get latched in the
PS-XADC interface devcfg.XADCIF_INT_STS register and it can be used to determine which alarm was
activated. Writing a 1 to the active alarm bit in the devcfg.XADCIF_INT_STS register clears the
interrupt. The unmasked status of the alarm signals can be read using the devcfg.XADCIF_MSTS
register.