User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 753
UG585 (v1.11) September 27, 2016
Chapter 30: XADC Interface
The XADC serial clock drives the DCLK that is described in the LogiCORE User Guide.
30.3.2 Command and Data Packets
The PS-XADC interface buffers the 32-bit reads and writes to minimize the effects of the slow serial
transfer process on PS system throughput. The PS-XADC interface buffers up to 15 commands. Each
command is serialized and communicated to the XADC. For every command that is written to the
PS-XADC interface, a data word is received in the Read Data FIFO. The Read Data FIFO can store 15
data words. Up to 15 commands at a time to be written and up to 15 read data words can be in
FIFOs. After a read command has been written, the corresponding read data is available after the
next command is serialized to the XADC, see Figure 30-3. Therefore, if the last command in CMD FIFO
is a read command, one additional NOP command is always needed to push out the last read data.
The XADC commands are listed in the LogiCORE user guide and in UG480,
7 Series FPGAs and
Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide.
All control commands, read requests, write requests, and NOPs shift data into the Read Data FIFO
that can be read using the devcfg.XADCIF_RDFIFO register. The software controlling the PS-XADC
interface should account for this and should read and discard data not generated by a read
command. XADC read data is 32-bits but only the 16 LSBs of the 32-bit word contain ADC data.
PS-XADC Event Timing
•Command register write
• Serialized to XADC (control and data)
• Programmable idle gap width, devcfg.XADCIF_CFG [IGAP]
The status of the command and Read Data FIFOs can be monitored using the devcfg.XADCIF_MSTS
Interface Miscellaneous S
tatus register. Software can also setup interrupts using the
devcfg.XADCIF_INT_STS Interrupt Status register.
X-Ref Target - Figure 30-3
Figure 30-3: XADC PS-XADC Interface Event Timing Diagram
UG585_c30_11_022513
n
Write Sequence to the Command FIFO
n + 1
PS_TDO Signal
(commands)
PS_TDI Signal
(results)
Command is processed
by the XADC.
n - 1
n + 2
n n +1
Dummy
Data or Previous
Command Result
Dummy
Data
Second
Command
First
Command
Result from
First
Command
Result from
Second
Command
Command is processed
by the XADC.
Reads from
Data Read FIFO
Idle Gap
Time
32-bit
32 bits
32-bit