User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 755
UG585 (v1.11) September 27, 2016
Chapter 30: XADC Interface
30.3.5 Min/Max Voltage Thresholds
The XADC tracks the minimum and maximum values recorded for the internal supply sensors since
the last power-up or the last reset of the XADC control logic. The maximum and minimum values
recorded are stored in the DRP Status registers. On power-up or after reset, all Minimum registers are
set to FFFFh and all Maximum registers are set to 0000h. Each new measurement generated for an
on-chip sensor is compared to the contents of its Maximum and Minimum register. If the measured
value is greater than the contents of it Maximum register, the measured value is written to the
Maximum register. Similarly, for the Minimum register, if the measured value is less than the contents
of its Minimum register, the measured value is written to the Minimum register. This check is carried
out each time a measurement result is written to the Status register.
30.3.6 Critical Over-temperature Alarm
Note: This feature sends an interrupt status to the PS and causes an automatic shutdown feature for
the PL side of the Zynq-7000 device if enabled. The PL shutdown is enabled via the bitstream and the
PL will only come out of power-down if the over-temperature alarm goes inactive or a
reconfiguration occurs.
The on-chip temperature measurement is used for critical temperature warnings. The default over
temperature threshold is 125°C. This threshold is used when the contents of the OT Upper Alarm
register (listed in UG480) have not been
conf
igured. When the die temperature exceeds the
threshold set in the XADC’s Control register, the over-temperature alarm (OT) becomes active. The OT
signal resets when the die temperature has fallen below set threshold.
The OT alarm can also be used to automatically power down the PL upon activation. The OT alarm can
be disabled by writing a
1
to the OT bit in the XADC’s
Conf
iguration register.
Note: these registers are in the XADC and are accessible using the DRP.
The XADC OT alarm signal is sent to the PS via the dedicated PS-XADC interface. When the OT alarm
goes active it triggers a maskable interrupt. The OT bit of the XADCIF_INT_STS register needs to be
cleared by writing a
1
to the bit location. The real time value of the OT alarm signal can be found on the
XADCIF_MSTS register.
30.4 Programming Guide for the PS-XADC Interface
The following sequence describes how to configure and interact with the PS-XADC interface to read
an internal VCC auxiliary PS voltage (V
CCPAUX
) and raise an Alarm interrupt when V
CCPAUX
value does
not fall between higher and lower thresholds. The PS-XADC interface specifies commands to be sent
in a specific format as described in section 30.3.3 Command Format. Refer to detailed examples in
section 30.4.3 Command Preparation.
Example: Initialization of XADC via the PS-XADC Interface
This example resets the communications channel and the XADC. It also flushes the FIFOs; leaving a
NOOP (dummy) word in the XADC.