User manual
Table Of Contents
- Zynq-7000 All Programmable SoC
- Table of Contents
- Ch. 1: Introduction
- Ch. 2: Signals, Interfaces, and Pins
- Ch. 3: Application Processing Unit
- Ch. 4: System Addresses
- Ch. 5: Interconnect
- Ch. 6: Boot and Configuration
- Ch. 7: Interrupts
- Ch. 8: Timers
- Ch. 9: DMA Controller
- Introduction
- Functional Description
- DMA Transfers on the AXI Interconnect
- AXI Transaction Considerations
- DMA Manager
- Multi-channel Data FIFO (MFIFO)
- Memory-to-Memory Transfers
- PL Peripheral AXI Transactions
- PL Peripheral Request Interface
- PL Peripheral - Length Managed by PL Peripheral
- PL Peripheral - Length Managed by DMAC
- Events and Interrupts
- Aborts
- Security
- IP Configuration Options
- Programming Guide for DMA Controller
- Programming Guide for DMA Engine
- Programming Restrictions
- System Functions
- I/O Interface
- Ch. 10: DDR Memory Controller
- Introduction
- AXI Memory Port Interface (DDRI)
- DDR Core and Transaction Scheduler (DDRC)
- DDRC Arbitration
- Controller PHY (DDRP)
- Initialization and Calibration
- DDR Clock Initialization
- DDR IOB Impedance Calibration
- DDR IOB Configuration
- DDR Controller Register Programming
- DRAM Reset and Initialization
- DRAM Input Impedance (ODT) Calibration
- DRAM Output Impedance (RON) Calibration
- DRAM Training
- Write Data Eye Adjustment
- Alternatives to Automatic DRAM Training
- DRAM Write Latency Restriction
- Register Overview
- Error Correction Code (ECC)
- Programming Model
- Ch. 11: Static Memory Controller
- Ch. 12: Quad-SPI Flash Controller
- Ch. 13: SD/SDIO Controller
- Ch. 14: General Purpose I/O (GPIO)
- Ch. 15: USB Host, Device, and OTG Controller
- Introduction
- Functional Description
- Programming Overview and Reference
- Device Mode Control
- Device Endpoint Data Structures
- Device Endpoint Packet Operational Model
- Device Endpoint Descriptor Reference
- Programming Guide for Device Controller
- Programming Guide for Device Endpoint Data Structures
- Host Mode Data Structures
- EHCI Implementation
- Host Data Structures Reference
- Programming Guide for Host Controller
- OTG Description and Reference
- System Functions
- I/O Interfaces
- Ch. 16: Gigabit Ethernet Controller
- Ch. 17: SPI Controller
- Ch. 18: CAN Controller
- Ch. 19: UART Controller
- Ch. 20: I2C Controller
- Ch. 21: Programmable Logic Description
- Ch. 22: Programmable Logic Design Guide
- Ch. 23: Programmable Logic Test and Debug
- Ch. 24: Power Management
- Ch. 25: Clocks
- Ch. 26: Reset System
- Ch. 27: JTAG and DAP Subsystem
- Ch. 28: System Test and Debug
- Ch. 29: On-Chip Memory (OCM)
- Ch. 30: XADC Interface
- Ch. 31: PCI Express
- Ch. 32: Device Secure Boot
- Appx. A: Additional Resources
- Appx. B: Register Details
- Overview
- Acronyms
- Module Summary
- AXI_HP Interface (AFI) (axi_hp)
- CAN Controller (can)
- DDR Memory Controller (ddrc)
- CoreSight Cross Trigger Interface (cti)
- Performance Monitor Unit (cortexa9_pmu)
- CoreSight Program Trace Macrocell (ptm)
- Debug Access Port (dap)
- CoreSight Embedded Trace Buffer (etb)
- PL Fabric Trace Monitor (ftm)
- CoreSight Trace Funnel (funnel)
- CoreSight Intstrumentation Trace Macrocell (itm)
- CoreSight Trace Packet Output (tpiu)
- Device Configuration Interface (devcfg)
- DMA Controller (dmac)
- Gigabit Ethernet Controller (GEM)
- General Purpose I/O (gpio)
- Interconnect QoS (qos301)
- NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
- I2C Controller (IIC)
- L2 Cache (L2Cpl310)
- Application Processing Unit (mpcore)
- On-Chip Memory (ocm)
- Quad-SPI Flash Controller (qspi)
- SD Controller (sdio)
- System Level Control Registers (slcr)
- Static Memory Controller (pl353)
- SPI Controller (SPI)
- System Watchdog Timer (swdt)
- Triple Timer Counter (ttc)
- UART Controller (UART)
- USB Controller (usb)
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 756
UG585 (v1.11) September 27, 2016
Chapter 30: XADC Interface
1. Reset the serial communication channel. Write a 1 and then a 0 to devcfg.XADCIF_MCTL
[RESET].
2. Reset the XADC. Write any 16-bit value to DRP address 0x03 (reset register). Write 08030000h
to the devcfg.XADCIF_CMDFIFO register.
3. Flush the FIFOs. There is no reset signal, instead write 15 NOOPs to the FIFO:
a. Wait for the Command FIFO to empty. The last command should be a NOOP (dummy write).
b. Read the Read Data FIFO until empty.
Example: Start-up Sequence via the PS-XADC Interface
This example sets various interface parameters and includes steps for interrupts and data transfers. It
assumes the interface and the XADC are already initialized.
1. Configure the PS-XADC interface: Program the configuration register. Write 80001114h into
the devcfg.XADCIF_CFG register:
a. Use default Minimum idle gap, [IGAP] = 14h (20 serial clocks).
b. Use default XADC serial clock frequency to 1/4 of PCAP_2x clock frequency, [TCKRATE] = 01.
c. Use default FIFO serial read capture edge (rising), [REDGE] = 1.
d. Use default FIFO serial write launch edge (falling), [WEDGE] = 0.
e. Use default Read Data FIFO threshold level, [DFIFOTH] = 0x0.
f. Use default Command FIFO threshold level, [CFIFOTH] = 0.
g. Enable the PS access of XADC. Write 0x1 to devcfg.XADCIF_CFG [ENABLE].
2. Configure the interrupts: Interrupts are used to manage the alarms from the XADC and
Command/Read Data FIFOs. Refer to the program example in section 30.5.3 Interrupts.
3. Data transfers to the XADC: Refer to section 30.5.2 Read and Write FIFOs.
30.4.1 Read and Write to the FIFOs
This example configures the devcfg.XADCIF_CFG register for the FIFOs and communications channel.
This register controls the command and Read Data FIFO thresholds, the clock rate of the
XADC_PS_TCK, the clocking edges for the serial bus and the idle gap between serial packets.
After power on Command and Read Data FIFOs of the PS-XADC interface are empty, but must be
flushed after an XADC interface reset. Commands for writing to or reading from XADC registers are
sent to the XADC using the Command FIFO, and data returned from the XADC is collected in the Read
Data FIFO.
Example: Write Command to the XADC
This example writes to the XADC V
CCPAUX
Alarm Upper threshold register.
1. Prepare command. Prepare the command as described in section 30.4.3 Command Preparation
for writing to the XADC V
CCPAUX
Alarm Upper threshold register (0x5A) with required threshold.
2. Fill the Command FIFO with data. Write the data formatted in step 1 to the
devcfg.XADCIF_CMDFIFO register.